音乐分频.txt

十二音阶和八度分频的硬件描述语言VHDL程序

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:27:07 04/13/2009 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
   port(clk2MHz :in std_logic;
	     yinjie: in std_logic_vector(3 downto 0);
		  du8:    in std_logic_vector(1 downto 0);
		  fout:   out std_logic);
end top;

architecture Behavioral of top is
component fenpin4
        Port ( clk : in  STD_LOGIC;
           fout0 : out  STD_LOGIC);
end component;
component yinjie12 
    Port ( clk500K : in  STD_LOGIC;
           p : in  STD_LOGIC_vector(3 downto 0);
           fout1 : out  STD_LOGIC);
end component;
component du_8
port(clk16: in std_logic;
       q: in std_logic_vector(1 downto 0);
	 fout2: out std_logic);
end component;
signal temp1,temp2:std_logic;
begin
u0:fenpin4 port map(clk=>clk2MHz,fout0=>temp1);
u1:yinjie12 port map(clk500K=>temp1,p=>yinjie,fout1=>temp2);
u3:du_8 port map(clk16=>temp2,q=>du8,fout2=>fout);
end Behavioral;







----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:46:24 04/13/2009 
-- Design Name: 
-- Module Name:    4fenpin - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fenpin4 is
    Port ( clk : in  STD_LOGIC;
           fout0 : out  STD_LOGIC);
end fenpin4;

architecture Behavioral of fenpin4 is
begin
process(clk)
variable count:integer range 0 to 8;
begin
if clk'event and clk='1' then count:=count+1;
   if count=2 then fout0<='1';
	elsif count=4 then fout0<='0';count:=0;
	end if;
end if;
end process; 
end Behavioral;









----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:53:19 04/13/2009 
-- Design Name: 
-- Module Name:    12yinjie - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity yinjie12 is
    Port ( clk500K : in  STD_LOGIC;
            p : in  STD_LOGIC_vector(3 downto 0);
           fout1 : out  STD_LOGIC);
end yinjie12;

architecture Behavioral of yinjie12 is
signal count:integer range 0 to 255;
begin
process(clk500K,p)
variable cnt:integer range 0 to 255;
begin
  case p is
       when "0001"=>count<=239;
		 when "0010"=>count<=225;
		 when "0011"=>count<=213;
		 when "0100"=>count<=201;
		 when "0101"=>count<=190;
		 when "0110"=>count<=182;
		 when "0111"=>count<=169;
		 when "1000"=>count<=159;
		 when "1001"=>count<=150;
		 when "1010"=>count<=142;
		 when "1011"=>count<=134;
		 when "1100"=>count<=127;
		 when others=>count<=255;
	end case;
	if clk500K'event and clk500K='1' then cnt:=cnt+1;
	   if cnt=count/2 then fout1<='1';
		elsif cnt=count then fout1<='0';cnt:=0;
		end if;
	end if;
end process;

end Behavioral;









----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:50:26 04/13/2009 
-- Design Name: 
-- Module Name:    8du - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity du_8 is
port(clk16: in std_logic;
       q: in std_logic_vector(1 downto 0);
	 fout2: out std_logic);
end du_8;

architecture Behavioral of du_8 is
begin
process(clk16,q)
variable cnt:integer range 0 to 16;
begin
if q="00" then
   if clk16'event and clk16='1' then cnt:=cnt+1;
       if cnt=1 then fout2<='1';
		 elsif cnt=2 then fout2<='0';cnt:=0;
		 end if;
	end if;
elsif q="01" then
   if clk16'event and clk16='1' then cnt:=cnt+1;
       if cnt=2 then fout2<='1';
		 elsif cnt=4 then fout2<='0';cnt:=0;
		 end if;
	end if;
elsif q="10" then
   if clk16'event and clk16='1' then cnt:=cnt+1;
       if cnt=4 then fout2<='1';
		 elsif cnt=8 then fout2<='0';cnt:=0;
		 end if;
	end if;	  
else 
   if clk16'event and clk16='1' then cnt:=cnt+1;
       if cnt=1 then fout2<='1';
		 elsif cnt=2 then fout2<='0';cnt:=0;
		 end if;
	end if;
end if;
end process;
end Behavioral;