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📁 scmRTOS is real-time preemptive operating system and supports up to 31 user processes (and one syste
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<title>scmRTOS - Port for ARM7</title>
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        <div id="breadcrumbs"><a href="../../index.html">Main page</a>&nbsp;> <a href="../index.html">PORTs</a>&nbsp;> ARM7</div>
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        <h1>Port for ARM7 (common issues)</h1><p><strong>IAR Embedded Workbench</strong></p>
<div class="contents topic">
<p class="topic-title first"><a id="table-of-contents" name="table-of-contents">Table of Contents</a></p>
<ul class="simple">
<li><a class="reference" href="#general" id="id1" name="id1">General</a></li>
<li><a class="reference" href="#program-control-flow-transfer" id="id2" name="id2">Program Control Flow Transfer</a></li>
<li><a class="reference" href="#interrupts" id="id3" name="id3">Interrupts</a></li>
<li><a class="reference" href="#system-timer" id="id4" name="id4">System Timer</a></li>
<li><a class="reference" href="#summary" id="id5" name="id5">Summary</a></li>
</ul>
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<div class="section">
<h1><a class="toc-backref" href="#id1" id="general" name="general">General</a></h1>
<p>ARM7 is 32-bit RISC von Neumann processor. As user processes runs in System mode,
16 registers accessible by process:</p>
<table border="1" class="borderless marklist docutils">
<colgroup>
<col width="72%" />
<col width="28%" />
</colgroup>
<tbody valign="top">
<tr><td><ul class="first last simple">
<li>1 register is Status Register</li>
</ul>
</td>
<td>-  <strong>CPSR</strong>;</td>
</tr>
<tr><td><ul class="first last simple">
<li>1 register is R15, Program Counter</li>
</ul>
</td>
<td>-  <strong>PC</strong>;</td>
</tr>
<tr><td><ul class="first last simple">
<li>1 register is R14, Link Register</li>
</ul>
</td>
<td>-  <strong>LR</strong>;</td>
</tr>
<tr><td><ul class="first last simple">
<li>1 register is R13, Stack Pointer</li>
</ul>
</td>
<td>-  <strong>SP</strong>;</td>
</tr>
<tr><td><ul class="first last simple">
<li>13 general purpose registers R0-R12</li>
</ul>
</td>
<td>-  <strong>GPR</strong>.</td>
</tr>
</tbody>
</table>
<p>Therefore, context in the processor consists of:</p>
<blockquote>
13 (GPR) + 1 (PC) + 1 (LR) + 1 (CPSR) = 16 registers or 16*4 = 64 bytes.</blockquote>
<p>This means that each user's process must have stack greater at least
context size (64 bytes) + call depth multiplied by 4. SP register contents
stored in kernel's process table.</p>
<p>The Port uses one common stack for data and return addresses.</p>
</div>
<hr class="docutils" />
<div class="section">
<h1><a class="toc-backref" href="#id2" id="program-control-flow-transfer" name="program-control-flow-transfer">Program Control Flow Transfer</a></h1>
<p>Both methods - direct and software interrupt - are supported in the ARM7 port,
except ADuC port, where only direct method is supported because of absence
of interrupt controller.</p>
<p>In case of direct program control flow transfer there are no any peculiarities.</p>
<p>In case of software interrupt program control flow transfer a situation is the
following: if interrupt controller has dedicated software interrupt, this interrupt is used
(as in LPC2xxx port). If there is no special software interrupt, one of unused
hardware interrupts has been used. Any scmRTOS release has default Software
Context Switch interrupt assignment. The user can leave this default assignment
or change the assignment by analogy with defaults according to his project
requirements. This assignment is defined in project-dependent part of
the RTOS - <tt class="docutils literal"><span class="pre">scmRTOS_TARGET_CFG.h</span></tt> header file.</p>
</div>
<hr class="docutils" />
<div class="section">
<h1><a class="toc-backref" href="#id3" id="interrupts" name="interrupts">Interrupts</a></h1>
<p>The using of interrupts with scmRTOS does not make any special demands. The
user should keep in mind those things:</p>
<ul class="plain simple">
<li>only IRQ exception can use OS services, not FIQ.</li>
<li>IRQ exception handler implemented in <tt class="docutils literal"><span class="pre">scmRTOS_Target.s79</span></tt></li>
<li>interrupt service routine (ISR) functions must be qualified with <tt class="docutils literal"><span class="pre">OS_INTERRUPT</span></tt>
macro;</li>
<li><tt class="docutils literal"><span class="pre">TISRW</span></tt> object must be declared at the beginning of ISR which uses OS
services. This object involves constructor and destructor that play very
important role in the RTOS rescheduling mechanism and integrity.</li>
<li>in case of direct program control flow transfer ISR function which is not
uses OS services must be implemented in same way as ISR function which is
uses OS services.</li>
<li>in case of software interrupt program control flow transfer, ISR function
which is not uses OS services can be implemented in same way as ISR function
which is uses OS services, but it leads to some overhead in <tt class="docutils literal"><span class="pre">TISRW</span></tt> object
constructor and destructor. If overhead is undesirable, ISR function must
still be qualified with <tt class="docutils literal"><span class="pre">OS_INTERRUPT</span></tt> macro, but instead of declaring
<tt class="docutils literal"><span class="pre">TISRW</span></tt> object at the begining of ISR it must contain <tt class="docutils literal"><span class="pre">IRQ_DONE()</span></tt> macro
at the end of function.</li>
</ul>
<p>main() function stack (CSTACK) occupies the same space as IRQ stack (because
interrupts are disabled before RTOS starts). Therefore, this stack depth is
defined to be zero-sized in linker script. IRQ stack depth defined in linker
script by directive:</p>
<div class="line-block">
<div class="line"><tt class="docutils literal"><span class="pre">-DIRQ_STACK_SIZE=N</span></tt></div>
</div>
<p>where <tt class="docutils literal"><span class="pre">N</span></tt> - size of the stack.</p>
</div>
<hr class="docutils" />
<div class="section">
<h1><a class="toc-backref" href="#id4" id="system-timer" name="system-timer">System Timer</a></h1>
<p>scmRTOS v3 allows user to choose any available hardware timer, fully setup
the timer and setup interrupt vector of the timer. As Software Context Switch
interrupt assignment, any scmRTOS release has default timer assignment. The user
can leave this default assignment or change the assignment by analogy with defaults
according to his project requirements. All project-dependent definitions of System
Timer hardware implementation (setting, interrupt vector, etc.) resided in
project-dependent part of the RTOS - <tt class="docutils literal"><span class="pre">scmRTOS_TARGET_CFG.h</span></tt> header file.</p>
</div>
<hr class="docutils" />
<div class="section">
<h1><a class="toc-backref" href="#id5" id="summary" name="summary">Summary</a></h1>
<p>See <a class="reference" href="../../releases/index.html">Release info</a>
for more details about particulary chip family port features and
using examples.</p>
<p>As usual, see <a class="reference" href="../../doc/index.html">User's Manual</a> for more details
about RTOS contents, structure, functionality and features.</p>
</div>

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