📄 start91270.asm
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; ||||______ A4
; |||_______ A5
; ||________ A6
; |_________ A7
;
;
#set EPFUNCF B'00000000 ;<<< select address lines or general purpose port
; ||||||||
; ||||||||__ A8
; |||||||___ A9
; ||||||____ A10
; |||||_____ A11
; ||||______ A12
; |||_______ A13
; ||________ A14
; |_________ A15
;
;
;==============================================================================
; 4.6.7 Select External bus mode (Control signals)
;==============================================================================
; Select if the following ports are set to
; 0: External bus mode, I/O for control signals or
; 1: General purpose port
; By default these ports are set to External bus mode
;
#set EPFUNC3 B'00110000 ;<<< select address signals or general purpose port
; ||||||||
; ||||||||__ ASX
; |||||||___ RDX
; ||||||____ WR0X
; |||||_____ WR1X
; ||||______ BRQ (91280 only, else always '1')
; |||_______ BGRNTX (91280 only, else always '1')
; ||________ RDY
; |_________ SYSCLK
;
;
#set EPFUNC9 B'00000000 ;<<< select address signals or general purpose port
; ||||||||
; ||||||||__ CSX0
; |||||||___ CSX1
; ||||||____ CSX2
; |||||_____ CSX3
; ||||______ -
; |||_______ -
; ||________ -
; |_________ -
;
;==============================================================================
; 5 Section and Data Declaration
;==============================================================================
.export __start
.import _main
.import _RAM_INIT
.import _ROM_INIT
#if CLIBINIT == ON
.export __exit
.import _exit
.import __stream_init
#endif
#if CPLUSPLUS == ON
.export __abort
.import ___call_dtors
.import _atexit
#endif
;==============================================================================
; 5.1 Define Stack Size
;==============================================================================
.SECTION SSTACK, STACK, ALIGN=4
#if STACK_RESERVE == ON
.EXPORT __systemstack, __systemstack_top
__systemstack:
.RES.B STACK_SYS_SIZE
__systemstack_top:
#endif
.SECTION USTACK, STACK, ALIGN=4
#if STACK_RESERVE == ON
.EXPORT __userstack, __userstack_top
__userstack:
.RES.B STACK_USR_SIZE
__userstack_top:
#endif
;==============================================================================
; 5.2 Define Sections
;==============================================================================
.section DATA, data, align=4
.section INIT, data, align=4
.section CONST, const, align=4
.section INTVECT, const, align=4
#if CPLUSPLUS == ON
.section EXT_CTOR_DTOR, const, align=4 ; C++ constructors
#endif
;==============================================================================
;6. S T A R T
;==============================================================================
;-----------------------------------------------------------
; MACRO WAIT_LOOP
;-----------------------------------------------------------
#macro wait_loop loop_number
#local _wait64_loop
ldi #loop_number, r0
_wait64_loop:
add #-1, r0
bne _wait64_loop
#endm
.section CODE, code, align=4
.section CODE_START, code, align=4
__start: ; start point
ANDCCR #0xEF ; disable interrupts
STILM #LOW_PRIOR ; set interrupt level to low prior
;==============================================================================
; NOT RESET YET
;==============================================================================
startnop:
nop
; If the debugger stays at this NOP after download of application, the controller has
; not been reset yet. In order to reset all hardware registers it is
; highly recommended to reset the controller.
; However, if no reset is used on purpose, this start address can also be used.
; This mechanism is using the .END instruction at the end of this mo-
; dule. It is not necessary for controller operation but improves reliability
; of debugging (mainly emulator debugger). If the debugger stays here after a
; single step from label "_start" to label "startnop", the note can be ignored.
;==============================================================================
;6.1 Clock startup
;==============================================================================
#if (CLOCKSOURCE != NOCLOCK)
;==============================================================================
; 6.1.1 Set PLL Multiplier
;==============================================================================
LDI #0x0484, R0 ; Clock source control reg CLKR
LDI #(PLLSPEED << 4), R1 ; Use PLL x1, enable PLL
STB R1, @R0 ; store data to CLKR register
;==============================================================================
; 6.1.2 Start PLLs
;==============================================================================
#if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )
LDI #0x0484, R0 ; Clock source control reg CLKR
LDI #0x04, R1 ; Use PLL x1, enable PLL
ORB R1, @R0 ; store data to CLKR register
#endif
#if ENABLE_SUBCLOCK == ON
LDI #0x0484, R0 ; Clock source control reg CLKR
LDI #0x08, R1 ; enable subclock operation
ORB R1, @R0 ; store data to CLKR register
#endif
;==============================================================================
; 6.1.3 Wait for PLL oscillation stabilisation
;==============================================================================
#if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))
LDI #0x0482, R0 ; TimeBaseTimer TBCR
LDI #0x10, R1 ; set 256us
STB R1, @R0
LDI #0x90, R1 ; set interrupt flag for simulator
STB R1, @R0
LDI #0x0483, R0 ; clearTimeBaseTimer CTBR
LDI #0xA5, R1
STB R1, @R0
LDI #0x5A, R1
STB R1, @R0
LDI:20 #0x0482, R0
PLLwait:
BTSTH #8, @R0
BEQ PLLwait
#endif
;==============================================================================
; 6.1.4 Set clocks
;==============================================================================
;==============================================================================
; 6.1.4.1 Set CPU and peripheral clock
;==============================================================================
; CPU and peripheral clock are set in one register
LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB)
LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting
STB R3, @R2
;==============================================================================
; 6.1.4.2 Set External Bus interface clock
;==============================================================================
; set External Bus clock
; Be aware to do smooth clock setting, to avoid wrong clock setting
; Take care, always write 0 to the lower 4 bits of DIVR1 register
LDI #0x0487, R2 ; Set DIVR1
LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting
STB R3, @R2
;==============================================================================
; 6.1.4.3 Set CAN clock prescaler
;==============================================================================
; Set CAN Prescaler, only clock relevant parameter
LDI #0x01A8, R0 ; Set CAN ClockParameter Register
LDI #CANCLOCK, R1 ; Load Divider
STB R1, @R0 ; Set Divider
;==============================================================================
; 6.1.4.4 Switch Main Clock Mode
;==============================================================================
#if CLOCKSOURCE == MAINCLOCK
;==============================================================================
; 6.1.4.5 Switch Subclock Mode
;==============================================================================
#elif ( (CLOCKSOURCE == SUBCLOCK) )
#if ENABLE_SUBCLOCK == ON
LDI #0x0484, R0 ; Clock source control reg CLKR
LDI #0x01, R1 ; load value to select main clock
ORB R1, @R0 ; enable subclock as clock source
#else
#error: Wrong setting! The clock source is subclock, but the subclock is disabled.
#endif
;==============================================================================
; 6.1.4.6 Switch to PLL Mode
;==============================================================================
#elif ( (CLOCKSOURCE == MAINPLLCLOCK) )
LDI #0x0484, R0 ; Clock source control reg CLKR
BORL #0x2, @R0 ; enable PLL as clock source
#endif
#endif /* #endif CLOCKMODE != NOCLOCK */
;==============================================================================
;6.2 Set BusInterface
;==============================================================================
#if (EXTBUS)
;==============================================================================
;6.2.1 Set CS0
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