📄 start91270.asm
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; Do not set a divide ratio that exceeds the maximum operating frequency of the device.
; For the maximum permitted frequency, please refer to the hardware manual.
;
#set CLOCK_DIV1 0x00 ; clock = 1/1 source clock
#set CLOCK_DIV2 0x01 ; clock = 1/2 source clock
#set CLOCK_DIV3 0x02 ; clock = 1/3 source clock
#set CLOCK_DIV4 0x03 ; clock = 1/4 source clock
#set CLOCK_DIV5 0x04 ; clock = 1/5 source clock
#set CLOCK_DIV6 0x05 ; clock = 1/6 source clock
#set CLOCK_DIV7 0x06 ; clock = 1/7 source clock
#set CLOCK_DIV8 0x07 ; clock = 1/8 source clock
#set CLOCK_DIV9 0x08 ; clock = 1/9 source clock
#set CLOCK_DIV10 0x09 ; clock = 1/10 source clock
#set CLOCK_DIV11 0x0A ; clock = 1/11 source clock
#set CLOCK_DIV12 0x0B ; clock = 1/12 source clock
#set CLOCK_DIV13 0x0C ; clock = 1/13 source clock
#set CLOCK_DIV14 0x0D ; clock = 1/14 source clock
#set CLOCK_DIV15 0x0E ; clock = 1/15 source clock
#set CLOCK_DIV16 0x0F ; clock = 1/16 source clock
;
;
#set CPUCLOCK CLOCK_DIV1 ; <<< set clock divider for CPU clock, CLKB (max. 32 MHz)
;
#set PERCLOCK CLOCK_DIV1 ; <<< set clock divider for CLKP (max. 32 MHz)
;
#set EXTBUSCLOCK CLOCK_DIV2 ; <<< set External bus clock divider (max. 16 MHz)
;
;==============================================================================
; 4.5.4 Select CAN clock
;==============================================================================
; Select the CAN prescaler clock source and source clock divider
; Do not set a frequency that exceeds the maximum operating frequency of the device.
; For the maximum permitted frequency, please refer to the hardware manual.
;
#set CANCLOCK CLOCK_DIV2 ; <<< set prescaler CAN clock divider (max. 16 MHz)
; ; Divisors 1 to 10 are allowed
;
;==============================================================================
; 4.6 External Bus Interface
;==============================================================================
; Following set-up the Bus-Interface
;
#set EXTBUS OFF ; <<< Enable Extern Bus-Interface
;
;
;====================================================================
; 4.6.1 Select Chip mode
;====================================================================
;
; In order to change the chip mode, the mode vecor has to be changed.
; (vectors.c) ; <<< refer to vectors.c
;
;==============================================================================
; 4.6.2 Select Chipselect
;==============================================================================
;
#set CS0 ON ; <<< select Chipselect (ON/OFF)
#set CS1 OFF ; <<< select Chipselect (ON/OFF)
#set CS2 OFF ; <<< select Chipselect (ON/OFF)
#set CS3 OFF ; <<< select Chipselect (ON/OFF)
;
; Select used Chipselects.
; NOTE: Check Hardware Manual which Chipselect signals are available
; for the used series!
;
#set CSENABLE B'00000001 ; <<< enable Chipselects, (1: enabled, 0:disabled)
; ||||||||
; ||||||||__ CS0 bit, enable/disable CS0 (1/0)
; |||||||___ CS1 bit, enable/disable CS1 (1/0)
; ||||||____ CS2 bit, enable/disable CS2 (1/0)
; |||||_____ CS3 bit, enable/disable CS3 (1/0)
; ||||______ -, always 0
; |||_______ -, always 0
; ||________ -, always 0
; |_________ -, always 0
;==============================================================================
; 4.6.3 Set memory addressing for Chipselects
;==============================================================================
#set AREASEL0 0x0000 ; <<< set Starting address for CS0 A[32..16]
#set AREASEL1 0x0000 ; <<< set Starting address for CS1
#set AREASEL2 0x0000 ; <<< set Starting address for CS2
#set AREASEL3 0x0000 ; <<< set Starting address for CS3
;
; set starting address of each used Chipselect. Chipselects not used
; (not set to ON in 4.7.2) must not be set (setting ignored).
; NOTE: Just the upper 8-bit must be used A[23-16]
; e.g. when using start address 0x00080000 set 0x0008
;==============================================================================
; 4.6.4 Configure Chipselect Area
;==============================================================================
; Bit description:
; Configure the used Chipselect ACRx register
;
; TYP3 TYP2 TYP1 TYP0 Select access type of each CS
; 0 0 X X : Normal access (asynchronous SRAM, I/O,
; single/page/burst-ROM/FLASH)
; 0 1 X X : Address/data multiplexed (8bit or 16bit bus width only)
; 0 X X 0 : WAIT insertion by RDY disabled
; 0 X X 1 : WAIT insertion by RDY enabled
; 0 X 0 X : The WR0X pin to the WR3X pin are used as write strobes
; (WRX is fixed at H-Level)
; 0 X 1 X : setting not allowed
; 1 0 0 0 : setting not allowed
; 1 0 0 1 : setting not allowed
; 1 0 1 0 : setting not allowed
; 1 0 1 1 : setting not allowed
; 1 1 0 0 : setting not allowed
; 1 1 0 1 : setting not allowed
; 1 1 1 0 : setting not allowed
; 1 1 1 1 : mask area setting
;
;
; WREN: enable or disable write access
; 1: enabled, 0: disabled
;
;
; DBW0 : Set data bus width
; 0 : 8-bit (BYTE access)
; 1 : 16-bit (HALF-WORD access)
;
;
; ! For chip select 0 and 1 only !
; ASZ1 ASZ0 : Select memory size of each chipselect
; 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[23:16] bits)
; 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[23:17] bits)
; 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[23:18] bits)
; 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[23:19] bits)
; ! For chip select 2 and 3 only !
; ASZ1 ASZ0 : Select memory size of each chipselect
; 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[23:20] bits)
; 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[23:21] bits)
; 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[23:22] bits)
; 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[23] bit)
;
;==============================================================================
#set CONFIGCS0 B'0011010000000000 ; <<< Configure CS0, ACR register
#set CONFIGCS1 B'0000000000000000 ; <<< Configure CS1, ACR register
#set CONFIGCS2 B'0000000000000000 ; <<< Configure CS2, ACR register
#set CONFIGCS3 B'0000000000000000 ; <<< Configure CS3, ACR register
; || | | ||||
; || | | ||||__ TYP0 bit, TYP0-4 bits select access type
; || | | |||___ TYP1 bit
; || | | ||____ TYP2 bit
; || | | |_____ TYP3 bit
; || | |_______ WREN bit, enable/disable (1/0) Write access
; || |____________ DBW0 bit, DBWx select data bus width
; ||______________ ASZ0 bit, ASZx bits select address size of CS
; |_______________ ASZ1 bit
;
;==============================================================================
; 4.6.5 Set Wait cycles for Chipselects
;==============================================================================
; Bit description:
; set Waitstates for each chipselect area (CSx)
;
; W14 W13 W12 : First access wait cycle can be set (0-15 cycles)
; 0 0 0 : 0 Wait state
; 0 0 1 : 1 Auto-wait cycle
; 0 1 0 : 2 Auto-wait cycle
; ....
; 1 1 1 : 7 Auto wait cycles
;
; W06 : Read -> Write idle cycle selection
; 0 : 0 cycle
; 1 : 1 cycle
; The read->write cycle is set to prevent a collision between read
; and write data on the data bus when a write cycle follows a read cycle.
;
; W04 : select Write recovery cycle
; 0 : 0 cycle
; 1 : 1 cycle
; The write recovery cycle is set when controlling accesses to a device with
; a restriction on the interval between a write access and the next access.
;
; W02 : Address -> CSX Delay selection
; 0 : no delay selected
; 1 : delay selected
; When no delay is selected, CS0X to CS7X start being asserted at same time
; as ASX is asserted.
;
; W01 : CSX -> RDX/WRX setup extention cycle
; 0 : 0 cycle
; 1 : 1 cycle
; When 0 (0 cycle) is set, RDX/WR0X to WR3X/WRX is output fastest on the rising
; edge of the external-memory clock MCLK output established immediately after
; assertion of CSX. WR0X to WR3X/WRX may be delayed by 1 cycle or more depending
; on the state of the internal bus. When 1 (1 cycle) is set, output of all of
; RDX/WR0X to WR3X/WRX is always delayed by 1 cycle or more.
;
; W00 : RDY/WRX -> CSX hold extension cycle
; 0 : 0 cycle
; 1 : 1 cycle
; When 0 (0 cycle) is set, CS0X to CS3X are negated after the elapse of the
; hold delay from the rising edge of the external-memory clock MCLK output
; established after negation of RDX/WR0X to WR3X/WRX. When 1 (1 cycle) is set,
; CS0X to CS3X are delayed by 1 cycle while being negated.
;==============================================================================
#set WAITREG0 B'0111000001010011 ; <<< configure CS0 Waitstates, AWR register
#set WAITREG1 B'0000000000000000 ; <<< configure CS1 Waitstates, AWR register
#set WAITREG2 B'0000000000000000 ; <<< configure CS2 Waitstates, AWR register
#set WAITREG3 B'0000000000000000 ; <<< configure CS3 Waitstates, AWR register
; ||| | | |||
; ||| | | |||__ W00 bit, RDY/WRY-> CSX hold cycle
; ||| | | ||___ W01 bit, CSX -> RDX/WRX setup extension cycle
; ||| | | |____ W02 bit, Address -> CSX Delay selection
; ||| | |______ W04 bit, W04/W05 Write recovery cycle
; ||| |________ W06 bit, W06/07 Read -> Write idle cycle
; |||______________ W12 bit, ASZx bits select addressing size
; ||_______________ W13 bit, of CS
; |________________ W14 bit
;
;
;==============================================================================
; 4.6.6 Select External bus mode (Address lines 23:16)
;==============================================================================
; Select if the following ports are set to
; 0: External bus mode, I/O for address lines or
; 1: General purpose port
; By default these ports are set to External bus mode
;
#set EPFUNC2 B'00000000 ;<<< select address lines or general purpose port
; ||||||||
; ||||||||__ A16
; |||||||___ A17
; ||||||____ A18
; |||||_____ A19
; ||||______ A20
; |||_______ A21
; ||________ A22
; |_________ A23
;
;
#set EPFUNCE B'00000000 ;<<< select address lines or general purpose port
; ||||||||
; ||||||||__ A0
; |||||||___ A1
; ||||||____ A2
; |||||_____ A3
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