sysend.c

VXWORKS BSP开发包,初始化 驱动文件

* RETURNS: OK, or ERROR if interrupts could not be enabled.
*/

LOCAL STATUS sys557IntEnable
    (
    int	unit		/* unit number */
    )
    {
    FEI_RESOURCE *pReso = &feiResources [unit];
    UINT8 rotary = I80310_ROT_STAT_REG_RD();

    switch (pReso->boardType)
	{
	case PRO100B:		/* handle PRO100B LAN Adapter */
            if (pReso->slot == 5)
              intEnable (I80312INT_VEC_SPCIA); /* pci slot corresponds to J1 port */
            else if (pReso->slot == 6)
	      intEnable (I80312INT_VEC_SPCIB); /* pci slot corresponds to J5 port */
            else if (rotary != 0x07)           /* rotary switch not in position 7 - stand-alone backplane */
             {
              if (pReso->slot == 7)            /* pci slot corresponds to cyclone backplane J3 port */
                intEnable (I80312INT_VEC_SPCIC);
              else if (pReso->slot == 8)       /* pci slot corresponds to cyclone backplane J4 port */
                intEnable (I80312INT_VEC_SPCID);
             }
	    break;
	case I82559ER:		/* handle I82559ER LAN Adapter */
	    intEnable (I80312INT_VEC_ETHERNET);
	    break;

	default:
	    return (ERROR);
	}

    return (OK);
    }

/*******************************************************************************
*
* sys557IntDisable - disable 82557 interrupts
*
* This routine disables 82557 interrupts.  This may involve operations on
* interrupt control hardware.
*
* The 82557 driver calls this routine throughout normal operation to enter
* critical sections of code.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if interrupts could not be disabled.
*/

LOCAL STATUS sys557IntDisable
    (
    int	unit		/* unit number */
    )
    {
    FEI_RESOURCE *pReso = &feiResources [unit];
    UINT8 rotary = I80310_ROT_STAT_REG_RD();

    switch (pReso->boardType)
	{
	case PRO100B:		/* handle PRO100B LAN Adapter */
            if (pReso->slot == 5)
              intDisable (I80312INT_VEC_SPCIA);  /* pci slot corresponds to J1 port */
            else if (pReso->slot == 6)
              intDisable (I80312INT_VEC_SPCIB);  /* pci slot corresponds to J5 port */
            else if (rotary != 0x07)             /* rotary switch not in position 7 - stand-alone backplane */
             {
              if (pReso->slot == 7)              /* pci slot corresponds to cyclone backplane J3 port */
                intDisable (I80312INT_VEC_SPCIC);  
              else if (pReso->slot == 8)         /* pci slot corresponds to cyclone backplane J4 port */
                intDisable (I80312INT_VEC_SPCID);
             }
	    break;
	case I82559ER:		/* handle I82559ER LAN Adapter */
	    intDisable (I80312INT_VEC_ETHERNET);
	    break;

	default:
	    return (ERROR);
	}

    return (OK);
    }

/*******************************************************************************
*
* sys557eepromRead - read a word from the 82557 EEPROM
*
* RETURNS: the EEPROM data word read in.
*/

LOCAL UINT16 sys557eepromRead
    (
    int	unit,		/* unit number */
    int	location	/* address of word to be read */
    )
    {
    UINT32 iobase = feiResources[unit].iobaseCsr;
    UINT16 retval = 0;
    UINT16 dataval;
    volatile UINT16 dummy;
    int ix;

    sysOutWord (iobase + SCB_EEPROM, EE_CS);	/* enable EEPROM */

    /* write the READ opcode */
    for (ix = EE_CMD_BITS - 1; ix >= 0; ix--)
	{
        dataval = (EE_CMD_READ & (1 << ix)) ? EE_DI : 0;
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sysDelay ();	/* delay for one I/O READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval | EE_SK);
        sysDelay ();	/* delay for one I/O READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sysDelay ();	/* delay for one I/O READ cycle */
        }

    /* write the location */
    for (ix = EE_ADDR_BITS - 1; ix >= 0; ix--)
	{
        dataval = (location & (1 << ix)) ? EE_DI : 0;
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sysDelay ();	/* delay for one I/O READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval | EE_SK);
        sysDelay ();	/* delay for one I/O READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sysDelay ();	/* delay for one I/O READ cycle */
	dummy = sysInWord (iobase + SCB_EEPROM);
        }

    if ((dummy & EE_DO) == 0)		/* dummy read */
	;

    /* read the data */
    for (ix = EE_DATA_BITS - 1; ix >= 0; ix--)
	{
        sysOutWord (iobase + SCB_EEPROM, EE_CS | EE_SK);
        sysDelay ();	/* delay for one I/O READ cycle */
        retval = (retval << 1) |
	         ((sysInWord (iobase + SCB_EEPROM) & EE_DO) ? 1 : 0);
        sysOutWord (iobase + SCB_EEPROM, EE_CS);
        sysDelay ();	/* delay for one I/O READ cycle */
        }

    sysOutWord (iobase + SCB_EEPROM, 0x00);	/* disable EEPROM */

    return (retval);
    }

/*******************************************************************************
*
* sys557mdioRead - read MDIO
*
* RETURNS: read value
*/

LOCAL UINT32 sys557mdioRead
    (
    int	unit,		/* unit number */
    int phyId,		/* PHY ID */
    int location	/* location to read */
    )
    {
    UINT32 iobase = feiResources[unit].iobaseCsr;
    int timeout   = 64*4;	/* <64 usec. to complete, typ 27 ticks */
    int val;

    sysOutLong (iobase + SCB_MDI, 0x08000000 | (location<<16) | (phyId<<21));
    do {
    	sysDelay ();	/* delay for one I/O READ cycle */
    	val = sysInLong (iobase + SCB_MDI);
    	if (--timeout < 0)
    	    printf ("sys557mdioRead() timed out with val = %8.8x.\n", val);
        } while (! (val & 0x10000000));

    return (val & 0xffff);
    }

/*******************************************************************************
*
* sys557mdioWrite - write MDIO
*
* RETURNS: write value
*/

LOCAL UINT32 sys557mdioWrite
    (
    int unit,		/* unit number */
    int phyId,		/* PHY ID */
    int location,	/* location to write */
    int value		/* value to write */
    )
    {
    UINT32 iobase = feiResources[unit].iobaseCsr;
    int timeout   = 64*4;	/* <64 usec. to complete, typ 27 ticks */
    int val;

    sysOutLong (iobase + SCB_MDI,
		0x04000000 | (location<<16) | (phyId<<21) | value);
    do {
    	sysDelay ();	/* delay for one I/O READ cycle */
    	val = sysInLong (iobase + SCB_MDI);
    	if (--timeout < 0)
    	    printf ("sys557mdioWrite() timed out with val = %8.8x.\n", val);
        } while (! (val & 0x10000000));

    return (val & 0xffff);
    }

/*******************************************************************************
*
* sys557Show - shows 82557 configuration
*
* this routine shows (Intel Pro Express 100) configuration
*
* RETURNS: N/A
*/

void sys557Show
    (
    int	unit		/* unit number */
    )
    {
    FEI_RESOURCE *pReso = &feiResources [unit];
    UINT32 iobase       = pReso->iobaseCsr;
    UCHAR etheraddr[6];
    int ix;
    int iy;

    if (unit > IQ80310_MAX_END_DEVS)
	{
	printf ("Illegal unit number %d\n", unit);
	return;
	}

    if (pReso->boardType != PRO100B
        && pReso->boardType != I82559ER)
	{
	printf ("Unit %d not an FEI device\n", unit);
	return;
	}

    for (ix = 0, iy = 0; ix < 3; ix++)
	{
        etheraddr[iy++] = pReso->eeprom[ix];
        etheraddr[iy++] = pReso->eeprom[ix] >> 8;
        }

    if (pReso->boardType == PRO100B)
        printf ("82557(%d): Intel EtherExpress Pro 10/100 at %#8x ", unit, iobase);
    else
        printf ("82559ER(%d): Intel Integrated 10/100 Chip at %#8x ", unit, iobase);

    for (ix = 0; ix < 5; ix++)
    	printf ("%2.2X:", etheraddr[ix]);
    printf ("%2.2X\n", etheraddr[ix]);

    printf ("CSR mem base address = %x, Flash mem base address = %x\n",
	    pReso->membaseCsr, pReso->membaseFlash);

    if (pReso->boardType == PRO100B)
        {
        if (pReso->eeprom[3] & 0x03)
            printf ("Receiver lock-up bug exists -- enabling work-around.\n");

        printf ("Board assembly %4.4x%2.2x-%3.3d, Physical connectors present:",
	    pReso->eeprom[8], pReso->eeprom[9]>>8, pReso->eeprom[9] & 0xff);
        for (ix = 0; ix < 4; ix++)
	    if (pReso->eeprom[5] & (1 << ix))
	        printf ("%s", fei_connectors [ix]);

        printf ("\nPrimary interface chip %s PHY #%d.\n",
	    fei_phys[(pReso->eeprom[6]>>8)&7], pReso->eeprom[6] & 0x1f);
        if (pReso->eeprom[7] & 0x0700)
	    printf ("Secondary interface chip %s.\n",
		    fei_phys[(pReso->eeprom[7]>>8)&7]);
        }

    if (pReso->timeout < 0)
        {		/* Test optimized out. */
	printf ("Self test failed, status %8.8x:\n"
	        " Failure to initialize the 82557.\n"
	        " Verify that the card is a bus-master capable slot.\n",
	        pReso->pResults[1]);
	}
    else
        {
	printf ("General self-test: %s.\n"
	        " Serial sub-system self-test: %s.\n"
	        " Internal registers self-test: %s.\n"
	        " ROM checksum self-test: %s (%#8.8x).\n",
	        pReso->pResults[1] & 0x1000 ? "failed" : "passed",
	        pReso->pResults[1] & 0x0020 ? "failed" : "passed",
	        pReso->pResults[1] & 0x0008 ? "failed" : "passed",
	        pReso->pResults[1] & 0x0004 ? "failed" : "passed",
	        pReso->pResults[0]);
        }
    }

#endif /* INCLUDE_FEI82557END */

/* 250 Micro-Second delay */
static void sysEndDelay()
{
    volatile int i;

    for(i = 0; i < 10000;)
        i++;
}

#endif	/* INCLUDE_END */