sysend.c

VXWORKS BSP开发包,初始化 驱动文件

            psMemBase = pspciBus == 0?I80312_OUTBOUND_PRI_MEM_WIN:I80312_OUTBOUND_SEC_MEM_WIN;
            psIoBase = pspciBus == 0?I80312_OUTBOUND_PRI_IO_WIN:I80312_OUTBOUND_SEC_IO_WIN;

	    boardType = boardResources[ix].type;

	    /* update the END device table */
	    pRsrc = &(pciResources[pciDevice]);

	    if (pRsrc->configType == AUTO)
		{
		/* get memory base address and I/O base address */
#ifdef INCLUDE_FEI82557END
		if ((boardType >= FEI_START) &&
 		    (boardType < (FEI_START + TYPE_ALLOC)))
                    {
                    pFeiRes = &feiResources [unit];

                    pciConfigInLong (pciBus, pciDevice, pciFunc,
                                     PCI_CFG_BASE_ADDRESS_0, (int *)&membaseCsr);

                    pciConfigInLong (pciBus, pciDevice, pciFunc,
                                     PCI_CFG_BASE_ADDRESS_1, (int *)&iobaseCsr);

                    pciConfigInByte (pciBus, pciDevice, pciFunc, 
                                     PCI_CFG_DEV_INT_LINE, &irq);

                    /* overwrite the resource table with read value */
                    pFeiRes->membaseCsr = (membaseCsr&I80312_OUTBOUND_MEM_MASK) | psMemBase;
                    iobaseCsr &= ~IO_SPACE_ENABLE;
                    pFeiRes->iobaseCsr = (iobaseCsr&I80312_OUTBOUND_IO_MASK) | psIoBase;
                    pFeiRes->irq = irq;
                    pFeiRes->configType = boardType;
                    pFeiRes->bus = pciBus;
                    pFeiRes->slot = pciDevice;
                    }
#endif	/* INCLUDE_FEI82557END */
		}
	    else		/* Force PCI configuration */
		{
#ifdef INCLUDE_FEI82557END
		if ((boardType >= FEI_START) &&
 		    (boardType < (FEI_START + TYPE_ALLOC)))
                    {
                    pFeiRes = &feiResources [unit];

                    pciConfigOutLong (pciBus, pciDevice, pciFunc, PCI_CFG_BASE_ADDRESS_0,
				      (pRsrc->membaseCsr&I80312_OUTBOUND_MEM_MASK) | 
                                      (pspciBus == 0?(*ATU_POMWVR):(*ATU_SOMWVR)));
                    pFeiRes->membaseCsr = pRsrc->membaseCsr;
                    pciConfigOutLong (pciBus, pciDevice, pciFunc, PCI_CFG_BASE_ADDRESS_1,
				      ((pRsrc->iobaseCsr &I80312_OUTBOUND_IO_MASK) | 
                                      (pspciBus == 0?(*ATU_POIOWVR):(*ATU_SOIOWVR)))
                                          | IO_SPACE_ENABLE);
                    pFeiRes->iobaseCsr = pRsrc->iobaseCsr;
                    pciConfigOutByte (pciBus, pciDevice, pciFunc,
                                      PCI_CFG_DEV_INT_LINE, pRsrc->irq);
                    pFeiRes->irq = pRsrc->irq;
		    }
#endif	/* INCLUDE_FEI82557END */
		}
	    /*
	     * Update the END device table & dynamically create the load
	     * string we need for this device
	     */
#ifdef INCLUDE_FEI82557END
            if ((boardType >= FEI_START) &&
                (boardType < (FEI_START + TYPE_ALLOC)))
                {
                strcpy (endLoadStr[currentEndDevice],
                        "-1:0x00:0x20:0x20:0x00:2");

                endDevTbl[currentEndDevice].unit = unit++;

                endDevTbl[currentEndDevice].endLoadFunc = fei82557EndLoad;

                endDevTbl[currentEndDevice].endLoadString =
                                                endLoadStr[currentEndDevice];
                endDevTbl[currentEndDevice].endLoan = 1;

                currentEndDevice++;

                /* enable mapped I/O addresses */
                pciConfigOutWord (pciBus, pciDevice, pciFunc,
                          PCI_CFG_COMMAND, IO_SPACE_ENABLE |
                          BUS_MASTER_ENABLE);

		/* disable sleep mode */
		pciConfigOutByte (pciBus, pciDevice, pciFunc, PCI_CFG_MODE,
				  SLEEP_MODE_DIS);
		}
#endif	/* INCLUDE_FEI82557END */

	    /* Configured the maximum number of adaptors? */
	    if (currentEndDevice == IQ80310_MAX_END_DEVS)
		{
		return OK;
		}
	    }
	}

    if ((unit == 0) || (pciDevice > PCI_MAX_DEV))
	{
	return (ERROR);
	}

    return (OK);
    }

#ifdef INCLUDE_FEI82557END
/*******************************************************************************
*
* sys557Init - prepare LAN adapter for 82557 initialization
*
* This routine is expected to perform any adapter-specific or target-specific
* initialization that must be done prior to initializing the 82557.
*
* The 82557 driver calls this routine from the driver attach routine before
* any other routines in this library.
*
* This routine returns the interrupt level the <pIntLvl> parameter.
*
* RETURNS: OK or ERROR if the adapter could not be prepared for initialization.
*/

STATUS sys557Init
    (
    int	unit,			/* unit number */
    FEI_BOARD_INFO *pBoard      /* board information for the end driver */
    )
    {
    volatile FEI_RESOURCE *pReso = &feiResources [unit];
    UINT16 sum          = 0;
    int	ix;
    int	iy;
    UINT16 value;
    void *testbuf = 0;    /* keep compiler quite */
    UCHAR *to_mac;
    UINT8 rotary = I80310_ROT_STAT_REG_RD();

    /* locate the 82557 based adapter. PRO100B and XXX */
    if (pReso->boardType != UNKNOWN)		/* only setup once */
	{
	}
    else
	{
	/* read the configuration in EEPROM */
    	for (ix = 0; ix < EE_SIZE; ix++)
    	    {
    	    value = sys557eepromRead (unit, ix);
    	    pReso->eeprom[ix] = value;
    	    sum += value;
    	    }
        if(pReso->configType == PRO100B)
            {
    	    if (sum != EE_CHECKSUM)
    	        printf ("i82557(%d): Invalid EEPROM checksum %#4.4x\n", unit, sum);
    
    	    /* DP83840 specific setup */
    	    if (((pReso->eeprom[6]>>8) & 0x3f) == DP83840)
    	        {
    	        int reg23 = sys557mdioRead (unit, pReso->eeprom[6] & 0x1f, 23);
    	        sys557mdioWrite (unit, pReso->eeprom[6] & 0x1f, 23, reg23 | 0x0420);
    	        }
            }
        if(pReso->configType == I82559ER && 
            ( pReso->eeprom[0] == 0xffff && pReso->eeprom[1] == 0xffff &&
              pReso->eeprom[2] == 0xffff ) )
            {
		to_mac = (UCHAR *)pReso->eeprom;
                for (ix = 0; ix < 6; ix++)
        	    to_mac[ix] = i82559erMacAddr[ix];
            }

    /* perform a system self-test. */
    pReso->timeout     = 16000;          /* Timeout for set-test. */

    /*
     * No specific area specified, so we assume that cacheDmaMalloc() will
     * return a pointer to a suitable area. If the data cache is on,
     * this will be page-aligned, but if the data cache is off, then we
     * will just get whatever malloc returns.
     */

    if (testbuf = cacheDmaMalloc (32), testbuf == 0)
     {
      printf("fei%d cacheDmaMalloc failed\n", unit);
      return ERROR;
     }
    pReso->pResults = (volatile INT32 *)testbuf;

    /* The chip requires the results buffer to be 16-byte aligned. */

    pReso->pResults    = (volatile INT32 *) ((((int) pReso->pResults) + 0xf) & ~0xf);

    pReso->pResults[0] = 0;
    pReso->pResults[1] = -1;

    /* Issue the self-test command */

    /*
     * If using cacheDmaMalloc() it will return a "low-alias" address in
     * SDRAM, and this will need converting to a "high-alias"
     * address, so it can be accessed from the PCI bus.
     */

    sysOutLong (pReso->iobaseCsr + SCB_PORT, (int)pReso->pResults | 1);

    /* wait for results */
    do
     {
      sysDelay (); /* cause a delay of at least an I/O cycle */
     } while ((pReso->pResults[1] == -1) && (--pReso->timeout >= 0));

    /* Save results so we can refer to them again later */

    pReso->str[0] = pReso->pResults[0];
    pReso->str[1] = pReso->pResults[1];

    cacheDmaFree (testbuf);

    pReso->pResults = pReso->str;

        if(pReso->configType == PRO100B)
            pReso->boardType = PRO100B;
        else
            pReso->boardType = I82559ER;
	}

    /* initializes the board information structure */
    if(pReso->configType == PRO100B)
     {
      if (pReso->slot == 5)
        pBoard->vector = I80312INT_VEC_SPCIA;  /* pci slot corresponds to J1 port */
      else if (pReso->slot == 6)
        pBoard->vector = I80312INT_VEC_SPCIB;  /* pci slot corresponds to J5 port */
      else if (rotary != 0x07)                 /* rotary switch not in position 7 - stand-alone backplane */
             {
              if (pReso->slot == 7)            /* pci slot corresponds to cyclone backplane J3 port */
                pBoard->vector = I80312INT_VEC_SPCIC;  
              else if (pReso->slot == 8)       /* pci slot corresponds to cyclone backplane J4 port */
                pBoard->vector = I80312INT_VEC_SPCID;  
             }
     }
    else
        pBoard->vector	  = I80312INT_VEC_ETHERNET;

    pBoard->baseAddr	  = pReso->iobaseCsr;
    for (ix = 0, iy = 0; ix < 3; ix++)
	{
	pBoard->enetAddr[iy++] = pReso->eeprom[ix] & 0xff;
	pBoard->enetAddr[iy++] = (pReso->eeprom[ix] >> 8) & 0xff;
	}
    pBoard->intEnable	  = sys557IntEnable;
    pBoard->intDisable	  = sys557IntDisable;
    pBoard->intAck	  = sys557IntAck;
    pBoard->sysLocalToBus = NULL;
    pBoard->sysBusToLocal = NULL;

#ifdef FEI_10MB
    pBoard->phySpeed	  = NULL;
    pBoard->phyDpx	  = NULL;
#endif

    return (OK);
    }

/*******************************************************************************
*
* sys557IntAck - acknowledge an 82557 interrupt
*
* This routine performs any 82557 interrupt acknowledge that may be
* required.  This typically involves an operation to some interrupt
* control hardware.
*
* This routine gets called from the 82557 driver's interrupt handler.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if the interrupt could not be acknowledged.
*/

LOCAL STATUS sys557IntAck
    (
    int	unit		/* unit number */
    )
    {
    FEI_RESOURCE *pReso = &feiResources [unit];

    switch (pReso->boardType)
	{
	    /* no addition work necessary for the PRO100B */
	case PRO100B:		/* handle PRO100B LAN Adapter */
	    break;
	case I82559ER:		/* handle I82559ER LAN Adapter */
	    break;

	default:
	    return (ERROR);
	}

    return (OK);
    }

/*******************************************************************************
*
* sys557IntEnable - enable 82557 interrupts
*
* This routine enables 82557 interrupts.  This may involve operations on
* interrupt control hardware.
*
* The 82557 driver calls this routine throughout normal operation to terminate
* critical sections of code.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*