📄 syslib.c
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sysEnableIRQMasks (); }/********************************************************************************* sysHwInit2 - additional system configuration and initialisation** This routine connects system interrupts and does any additional* configuration necessary.** RETURNS: N/A** NOMANUAL*/void sysHwInit2 (void) { /* Allocate vector table and init handlers */ intLibInit (I80312INT_MAX_LEVELS, I80312INT_MAX_LEVELS, I80312INT_MODE); /* initialise the interrupt controller */ i80312IntDevInit ();#if defined (INCLUDE_SERIAL) /* connect serial interrupt */ sysSerialHwInit2 ();#endif#if defined(INCLUDE_FEI82557END) /* map FEI Ethernet PCI device memory and I/O addresses */ sysLanPciInit ();#endif /* INCLUDE_FEI82557END */ }/********************************************************************************* sysPhysMemTop - get the address of the top of physical memory** This routine returns the address of the first missing byte of memory,* which indicates the top of memory.** Normally, the user specifies the amount of physical memory with the* macro LOCAL_MEM_SIZE in config.h. BSPs that support run-time* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the* true size of physical memory.** NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application* use. See sysMemTop() for more information on reserving memory.** RETURNS: The address of the top of physical memory.** SEE ALSO: sysMemTop()*/char *sysPhysMemTop (void) { static char * physTop = NULL; if (physTop == NULL) {#ifdef LOCAL_MEM_AUTOSIZE/* auto-sizing is possible */ physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + sysPhysMemSize ());#else/* Don't do autosizing, if size is given */ physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);#endif /* LOCAL_MEM_AUTOSIZE */ } return physTop; }/********************************************************************************* sysMemTop - get the address of the top of memory** This routine returns the address of the first missing byte of memory,* which indicates the top of memory.** RETURNS: The address of the top of memory.*/char *sysMemTop (void) {#ifdef LOCAL_MEM_AUTOSIZE/* auto-sizing is possible */ return ((char *)LOCAL_MEM_LOCAL_ADRS + (sysPhysMemSize () - LOCAL_MEM_RESERVED));#else/* Don't do autosizing, if size is given */ return ((char *)LOCAL_MEM_LOCAL_ADRS + (LOCAL_MEM_SIZE - LOCAL_MEM_RESERVED));#endif /* LOCAL_MEM_AUTOSIZE */ }/********************************************************************************* sysToMonitor - transfer control to the ROM monitor** This routine transfers control to the ROM monitor. It is usually called* only by reboot() -- which services ^X -- and bus errors at interrupt* level. However, in some circumstances, the user may wish to introduce a* new <startType> to enable special boot ROM facilities.** startType - passed to ROM to tell it how to boot** RETURNS: Does not return.*/STATUS sysToMonitor (int startType) { FUNCPTR pRom;#ifdef INCLUDE_PCI UINT32 tmp;#endif#if defined(INCLUDE_END) END_OBJ * pEnd; UINT32 i;#endif /* INCLUDE_END */ I80310_PAL_XINT3_INT_MASK_WR(0x1f); sysClkDisable();#if defined(INCLUDE_SERIAL) sysSerialReset (); /* put serial devices into quiet state */#endif#if defined(INCLUDE_END) /* * If the Ethernet driver were left alone, the controller chip might * alter memory, so we stop the controller before jumping to the bootrom. */ for(i = 0; i < PCI_MAX_DEV; i++) { if ( (pEnd = endFindByName ("fei", i)) != NULL) pEnd->pFuncTable->stop(pEnd->devObject.pDevice); }#endif /* INCLUDE_END */#ifdef INCLUDE_PCI /* Disable ATU */ /* Disable the devices */ *((volatile UINT16 *)(BRIDGE_PCR)) = (0x00); *((volatile UINT16 *)(ATU_PATUCMD)) = (0x00); *((volatile UINT16 *)(ATU_SATUCMD)) = (0x00); /* Disable Outbound Transactions */ tmp = *(volatile UINT32 *)(ATU_ATUCR); *((volatile UINT32 *)(ATU_ATUCR)) = (tmp & (~0x6)); /* mask off ATU error ints, we must disable all IRQ causes */ *((volatile UINT32 *)(ATU_PATUIMR)) = (0x1FD); *((volatile UINT32 *)(ATU_SATUIMR)) = (0x1FD);#endif intIFLock (); cacheArmXSCALEDClearDisable (); cacheArmXSCALEIClearDisable (); mmuArmXSCALETLBIDFlushAll (); mmuArmXSCALEADisable (); if (startType != BOOT_COLD) pRom = (FUNCPTR) (ROM_TEXT_ADRS + 4); /* warm boot */ else pRom = (FUNCPTR) ROM_TEXT_ADRS; /* cold boot */ (*pRom)(startType); /* jump to boot ROM */ return OK; /* in case we ever continue from ROM monitor */ }/*** BSP Info Routines ***//****************************************************************************** sysProcNumGet - get the processor number** This routine returns the processor number for the CPU board, which is* set with sysProcNumSet().** RETURNS: The processor number for the CPU board.** SEE ALSO: sysProcNumSet()*/int sysProcNumGet (void) { return sysProcNum; }/****************************************************************************** sysProcNumSet - set the processor number** Set the processor number for the CPU board. Processor numbers should be* unique on a single backplane.** NOTE* By convention, only processor 0 should dual-port its memory.** RETURNS: N/A** SEE ALSO: sysProcNumGet()*/void sysProcNumSet ( int procNum /* processor number */ ) { sysProcNum = procNum; }/********************************************************************************* sysModel - return the model name of the CPU board** This routine returns the model name of the CPU board.** RETURNS: A pointer to a string identifying the board and CPU.*/char *sysModel (void) { return "CyClone IQ80310 - I80200"; }/********************************************************************************* sysBspRev - return the bsp version with the revision eg 1.1/<x>** This function returns a pointer to a bsp version with the revision.* for eg. 1.1/<x>. BSP_REV is concatanated to BSP_VERSION to form the* BSP identification string.** RETURNS: A pointer to the BSP version/revision string.*/char * sysBspRev (void) { return (BSP_VERSION BSP_REV); }/********************************************************************************* iq80310BoardRev - returns board revision** RETURNS: the 4bit integer value contained in the board revision register*/int iq80310BoardRev (void) { return ((I80310_BRD_REV_REG_RD() & 0x0f)); /* bits #0-3 */ }/********************************************************************************* iq80310CPLDRev - returns CPLD revision** RETURNS: the 4bit integer value contained in the CPLD revision register*/int iq80310CPLDRev (void) { return((I80310_CPLD_REV_REG_RD() & 0x0f)); /* bits #0-3 */ }/* Wrappers *//********************************************************************************* sysIntDisable - disable a XINT3 interrupt level** This routine disables a specified XINT3 interrupt level.** .nT** RETURNS: OK, or ERROR if <intLevel> is out of range.** SEE ALSO: sysIntEnable(),* .sA*/STATUS sysIntDisable ( int intLevel /* interrupt level to disable */ ) { return (i80312IntLvlDisable (intLevel)); /* see i80312IntrCtl.c */ }/********************************************************************************* sysIntEnable - enable a XINT3 interrupt level** This routine enables a specified XINT3 interrupt level.** .nT** RETURNS: OK, or ERROR if <intLevel> is out of range.** SEE ALSO: sysIntDisable(),* .sA*/STATUS sysIntEnable ( int intLevel /* interrupt level to enable (1-7) */ ) { return (i80312IntLvlEnable (intLevel)); /* see i80312IntrCtl.c */ }/********************************************************************************* cacheDmaXMalloc - allocate a cache-safe buffer when X-bit set** cacheArchDmaMalloc returns the newly allocated buffer as non -cacheable,* since this violates the 80200 spec for X-bit usage we need to provide a* platform specific work around...** This routine attempts to return a pointer to a section of memory* that will not experience cache coherency problems. This routine* is only called when MMU support is available for cache control.** RETURNS: A pointer to a cache-safe buffer, or NULL.** NOMANUAL*/void * cacheDmaXMalloc ( size_t bytes /* size of cache-safe buffer */ ) { void * pBuf; int pageSize; if ((pageSize = VM_PAGE_SIZE_GET ()) == ERROR) return NULL;#if (!ARM_HAS_MPU) /* make sure bytes is a multiple of pageSize */ bytes = ROUND_UP (bytes, pageSize); if ((_func_valloc == NULL) || ((pBuf = (void *)(* _func_valloc) (bytes)) == NULL)) return NULL;#else /* (!ARM_HAS_MPU) */ /* * On MPUs, regions must be aligned with their size, which must be * a power of two and at least 4k in size. */ bytes = ROUND_UP (bytes, pageSize); /* round up to pageSize */ /* round up to a power of two in size */ bytes = ROUND_UP (bytes, (1 << (ffsMsb(bytes) - 1))); if ((_func_memalign == NULL) || ((pBuf = (void *)(* _func_memalign) (bytes, bytes)) == NULL)) return NULL;#endif /* !ARM_HAS_MPU) */ /* * Note that on MPUs we need to specify VM_STATE_VALID here, in * order that a new region will be created, if necessary, and that * that region will be marked as active, with appropriate access * rights. We should also free the allocate buffer and return NULL * if the VM_STATE_SET call fails. Here we set the cacheable & bufferable * bits under X-bit support. This fixes SPR #74186. */ if (VM_STATE_SET (NULL, pBuf, bytes, VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE | VM_STATE_MASK_VALID, VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE_NOT | VM_STATE_VALID) != OK) { free (pBuf); return NULL; } return pBuf; } /* cacheDmaXMalloc() */
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