syslib.c

VXWORKS BSP开发包,初始化 驱动文件

/* sysLib.c - IQ80310 EVal Board Specific routines */

/* Copyright 2000 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
02f,21jun02,scm modify sysToMonitor to disable ATU and reorder shutdown for
                proper reboot
02e,11mar02,scm spr #74186, provide dma malloc routine for use
                when exploiting the X-bit...
                cacheDmaXMalloc - allocate a cache-safe buffer when X-bit set
02d,26feb02,scm modify VirtToPhys/PhysToVirt for speedup of initialization...
02c,18jan02,scm re-org include defines...
02b,23jul01,scm change XScale name to conform to coding standards...
02a,16may01,jb  Removing FIQ support
01z,15may01,jb  Adding limited FIQ Support
01y,08may01,scm remove DEC21X40END references...
01x,01may01,scm add wrappers for sysIntDisable & sysIntEnable
01w,23apr01,scm remove warnings
01v,13apr01,scm disable interrupt sources not in use...
01u,21mar01,scm check board revisions...
01t,21feb01,scm add INCLUDE_FAST_DRAM support
01s,09feb01,scm set additional cache state "VM_STATE_BUFFERABLE_NOT"
01r,09feb01,scm add support for XScale minicache...
01q,26jan01,jb  Adding Flash as NvRam support
01p,23jan01,scm remove compiler warnings
01o,19jan01,scm debug tftp...
01n,18jan01,scm rework disabling of cache/MMU in sysToMonitor, add END
                support...
01m,11jan01,scm add support for sysPhysMemTop...
01l,04jan01,scm modify MMU initialization to reduce startup delay...
01k,18dec00,scm add BSP specific HW init routines
01j,12dec00,scm update memory map
01i,12dec00,scm correct cache settings
01h,11dec00,scm replace ARMSA2 with XScale...
01g,06dec00,jb  PCI/Lan Init complete
01f,06dec00,jb  removing Lan Init until debug finished
01e,06dec00,jb  Adding PCI Support
01d,29nov00,scm corrections made to PHYS_MEM_DESC
01c,28nov00,scm enable interrupts placed in sysHwInit
01b,23oct00,jb  Resolving all warnings
01a,05sep00,scm written
*/

/*
DESCRIPTION
This library provides board-specific routines.

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "stdio.h"
#include "usrLib.h"
#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"

#include "logLib.h"
#include "errnoLib.h"

#include "bootLib.h"
#include "vme.h"
#include "in.h"
#include "memLib.h"
#include "cacheLib.h"
#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"

/* Source Drivers */
#ifdef INCLUDE_FLASH
#include "mem/flashMem.c"
#include "mem/nvRamToFlash.c"
#else
#include "mem/nullNvRam.c"
#endif /* INCLUDE_FLASH */

#include "vme/nullVme.c"

#include "i80312IntrCtl.c"
#include "iq80310Timer.c"

#if defined (INCLUDE_SERIAL)
#include "sysSerial.c"
#endif

#if defined(INCLUDE_PCI)
#include "i80312PciLib.c"
#endif

#if defined(INCLUDE_END)
#include "sysEnd.c"
#endif

/* enable interrupts/fiqs on XScale */
extern void sysEnableIRQMasks ();

/* retrieve auto-sized memory */
extern UINT32 sysPhysMemSize ();

#if defined(INCLUDE_END)
/* find a device using its string name */
extern END_OBJ* endFindByName (char* pName, int unit);
#endif

/* externals */
IMPORT char end;		  	    /* end of system, created by ld */

IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */

IMPORT void i80312IntDevInit(void);

IMPORT STATUS i80312IntLvlEnable (int);
IMPORT STATUS i80312IntLvlDisable (int);

IMPORT void sysIntStackSplit (char *, long);

/* globals */
/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC or INCLUDE_MMU_FULL are
 * defined.
 *
 * The following are not the smallest areas that could be allocated for a
 * working system.  If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
/*
 * some sections conditionally removed because they are currently not necessary,
 * and to reduce the delay at startup...
 */
    { /* Init Boot Code From Flash Bank 1 */
    (void *) IQ80310_FLASH_BANK1_BASE,        /* virtual address */
    (void *) IQ80310_SDRAM_BASE_ADRS,         /* physical address */
    SZ_4K,                                    /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },
    { /* Peripheral Memory Mapped Registers */
    (void *) 0x00001000,                      /* virtual address */
    (void *) 0x00001000,                      /* physical address */
    SZ_4K,                                    /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },
    { /* Flash Bank 1 */
    (void *) 0x00002000,                      /* virtual address */
    (void *) 0x00002000,                      /* physical address */
    0x7FE000,                                 /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
#ifdef INCLUDE_FLASH
    /* needs to be writable */
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
#else
    VM_STATE_VALID      | VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT
#endif
    },
    { /* ATU Outbound Direct Addressing Windows */
    (void *) 0x00800000,                      /* virtual address */
    (void *) 0x00800000,                      /* physical address */
    0x7F800000,                               /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },
    { /* ATU Outbound Transaction Windows */
    (void *) 0x80000000,                      /* virtual address */
    (void *) 0x80000000,                      /* physical address */
    0x10020000,                               /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },
#if 0
    { /* RESERVED */
    (void *) 0x90020000,                      /* virtual address */
    (void *) 0x90020000,                      /* physical address */
    0xFFE0000,                                /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif
    { /* DRAM */
    (void *) IQ80310_SDRAM_BASE_ADRS,         /* virtual address */
    (void *) IQ80310_SDRAM_BASE_ADRS,         /* physical address */
    LOCAL_MEM_SIZE,                           /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },
#ifdef INCLUDE_FAST_DRAM
    { /* data cache fast dram option */
      /* No external memory request is made, which means software can map any
       * unallocated area of memory as data RAM. However, the line-allocate operation
       * does validate the target address with the MMU, so system software must ensure
       * that the memory has a valid descriptor in the page table.
       */
    (void *) FD_ORIGIN,                       /* virtual address */
    (void *) FD_ORIGIN,                       /* physical address */
    FD_MAX_SIZE,                              /* length (plus rounded-up), then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },
#endif
    { /* On-Board Devices */
    (void *) IQ80310_FLASH_BANK0_BASE,        /* virtual address */
    (void *) IQ80310_FLASH_BANK0_BASE,        /* physical address */
    0x100000,                                 /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#if 0
    { /* Flash Bank 0 */
    (void *) 0xfe900000,                      /* virtual address */
    (void *) 0xfe900000,                      /* physical address */
    0x1700000,                                /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
#ifdef INCLUDE_FLASH
    /* needs to be writable */
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
#else
    VM_STATE_VALID      | VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT
#endif
    }
#endif
};

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int  sysCpu = CPU;                   /* system CPU type */
char sysBootHost [BOOT_FIELD_LEN];   /* name of host from which we booted */
char sysBootFile [BOOT_FIELD_LEN];   /* name of file from which we booted */
int  sysFlags;                       /* boot flags */

int sysProcNum = 0;                  /* processor number of this CPU */
char *sysBootLine = BOOT_LINE_ADRS;  /* address of boot line */

/* Area used to flush D-cache */
UINT32 sysCacheFlushReadArea[D_CACHE_SIZE/sizeof(UINT32)];

/* Area used to flush mini-cache */
UINT32 sysMinicacheFlushReadArea[MINI_CACHE_SIZE/sizeof(UINT32)];

char *sysExcMsg   = EXC_MSG_ADRS;    /* catastrophic message area */

/* forward LOCAL function declarations */
/* forward declarations */
char *sysPhysMemTop (void);

void *cacheDmaXMalloc (size_t bytes);

/* iq80310 Board Rev Info... */
int iq80310BoardRev (void);
int iq80310CPLDRev (void);

/*** Init Routines ***/
/******************************************************************************
*
* iq80310_VirtToPhys - translate a virtual address to a physical address
*
* NOTE: This routine is dependent on the sysPhysMemDesc, if the one to one
*       mapping changes these routine will need modification...
*
*       The first 4K requires remapping in the form of:
*          return virtAddr - IQ80310_FLASH_BANK1_BASE + IQ80310_SDRAM_BASE_ADRS
*       since IQ80310_FLASH_BANK1_BASE = 0, it becomes:
*          return virtAddr + IQ80310_SDRAM_BASE_ADRS
*
* RETURNS: virtual address translated
*/

void * iq80310_VirtToPhys
    (
    void *      virtAddr        /* virtual address to be translated */
    )
    {

    if (virtAddr >= (void *)SZ_4K) /* we have a one-to-one mapping */
      return virtAddr;
    else
      return (void *)((UINT)virtAddr + (UINT)IQ80310_SDRAM_BASE_ADRS);

    }

/******************************************************************************
*
* iq80310_PhysToVirt - translate a physical address to a virtual address
*
* NOTE: This routine is dependent on the sysPhysMemDesc, if the one to one
*       mapping changes these routine will need modification...
*
*       The first 4K requires remapping in the form of:
*          return physAddr - IQ80310_SDRAM_BASE_ADRS + IQ80310_FLASH_BANK1_BASE
*       since IQ80310_FLASH_BANK1_BASE = 0, it becomes:
*          return physAddr - IQ80310_SDRAM_BASE_ADRS
*
* RETURNS: physical address translated
*/

void * iq80310_PhysToVirt
    (
    void *      physAddr        /* physical address to be translated */
    )
    {

    if (physAddr >= (void *)SZ_4K) /* we have a one-to-one mapping */
      return physAddr;
    else
      return (void *)((UINT)physAddr - (UINT)IQ80310_SDRAM_BASE_ADRS);

    }

/******************************************************************************
*
* sysHwInit0 - Intialize _func_armVirtToPhys before sysHwInit is called
*
* This function initialized _func_armVirtToPhys and _func_armPhysToVirt
* before sysHwInit is called. It is called from usrInit in bootConfig.c
* before cacheLibInit is called.
*
* RETURNS: N/A
*/

void sysHwInit0()
    {
#ifdef LOCAL_MEM_AUTOSIZE
    int i;
#endif

#if defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU)
    /*
     * Install the appropriate cache libary, using the our
     * address translation routines.
     */
    cacheArmXSCALELibInstall(iq80310_PhysToVirt, iq80310_VirtToPhys);
#endif

#ifdef INCLUDE_MMU
    /* Install the appropriate MMU library and translation routines */
    mmuArmXSCALELibInstall (iq80310_PhysToVirt, iq80310_VirtToPhys);
#endif /* INCLUDE_MMU */

#ifdef LOCAL_MEM_AUTOSIZE
    for (i = 0; i < sysPhysMemDescNumEnt; i++)
        {
        if ((sysPhysMemDesc[i].virtualAddr == (void *) IQ80310_SDRAM_BASE_ADRS) &&
            (sysPhysMemDesc[i].physicalAddr == (void *) IQ80310_SDRAM_BASE_ADRS))
                    sysPhysMemDesc[i].len = sysPhysMemSize();
        }
#endif
    }

/*******************************************************************************
*
* sysHwInit - initialise the CPU board hardware
*
* This routine initialises various features of the hardware.
* Normally, it is called from usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    /* Call back from the kernel for Interrupt stack setup */
    _func_armIntStackSplit = sysIntStackSplit;

    /* disable all interrupt sources */
    *(UINT32*)I80312_IIMR = 0x7f;
    /* INT_A is tied to pci port J1, and */
    /* INT_B is tied to pci port J5 */
    *(UINT32*)I80312_OIMR = 0x0f;

#if defined (INCLUDE_SERIAL)
    /* initialise the serial devices */
    sysSerialHwInit ();
#endif

#if defined(INCLUDE_PCI)
    sysPciInit();
#endif