i80312.h

VXWORKS BSP开发包,初始化 驱动文件

#define ISR_GCALL      0x0100      /* 1: I2C unit received a General Call address */
#define ISR_SADDR      0x0200      /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
#define ISR_ERROR      0x0400      /* Bit set by unit when a Bus Error detected */

#define ISAR_ADDR      0x00001688  /* Address of the I2C Slave Address Register */
#define IDBR_ADDR      0x0000168C  /* Address of the I2C Data Buffer Register */
#define IDBR_MASK      0x000000ff
#define IDBR_MODE      0x01
#define ICCR_ADDR      0x00001690  /* Address of the I2C Clock Control Register */
#define IBMR_ADDR      0x00001694  /* Address of the I2C Bus Monitor Register */

/* Codes for ROM bank size in bytes     */
#define ROM_0K          0
#define ROM_64K         1
#define ROM_128K        2
#define ROM_256K        3
#define ROM_512K        4
#define ROM_1M          5
#define ROM_2M          6
#define ROM_4M          7
#define ROM_8M          8
#define FWSR0_ADDR      0x0000155C  /* Flash Wait State 0 Register */
#define FWSR1_ADDR      0x00001560  /* Flash Wait State 1 Register */
#define MCISR_ADDR      0x00001564  /* Memory Controller Interrupt Status Register */
#define RFR_ADDR        0x00001568  /* Refresh Frequency Register */

/* ROM Memory Base Addresses for the PCI939 board */
#define ROM0_BASE_PCI939        0xFEE00000

/* Processor I2C Device ID */
#define I2C_DEVID       0x02  /* I2C slave address to which the unit responds when in slave-receive mode */

/* Timeout limit for SDRAM EEPROM to respond */
#define I2C_TIMOUT      0x1000000  /* bumped this way up...used to be 0x100000*/

#define SDRAM_DEVID     0xA2  /* SDRAM Device ID  */

/* SDRAM bank size values (SPD << 2) */
#define RAM_0MEG
#define RAM_4MEG    4
#define RAM_8MEG    8
#define RAM_16MEG   16
#define RAM_32MEG   32
#define RAM_64MEG   64
#define RAM_128MEG  128
#define RAM_256MEG  256

/* SBR register definitions (valid bits are [7:3])*/
#define SBR_32MEG   0x08
#define SBR_64MEG   0x10
#define SBR_128MEG  0x20
#define SBR_256MEG  0x40

/* Drive Strengths */
#define    SDCR_1BANK_X16       0x0AA0
#define    SDCR_2BANK_X16       0x12C8
#define    SDCR_1BANK_X8        0x1520
#define    SDCR_2BANK_X8        0x1548

/* SDRAM PD bytes                               */
#define BANKCNT_BYTE      0x06  /* Byte #5 of SPD: number of module banks */
#define SDRAM_WIDTH_BYTE  0x0E  /* Byte #13 of SPD: DRAM width indicator */
#define BANKSZ_BYTE       0x20  /* Byte #31 of SPD: module bank density */
#define CHECKSUM_BYTE     0x40  /* Byte #63 of SPD: checksum for bytes 0-62 */
#define CONFIG_BYTE       0x0C  /* Byte #11 of SPD: DIMM configuration type (Parity or not, EEC) */

#define    SZ_0       0x00000000
#define    SZ_1       0x00000001
#define    SZ_2       0x00000002
#define    SZ_4       0x00000004
#define    SZ_8       0x00000008
#define    SZ_16      0x00000010
#define    SZ_32      0x00000020
#define    SZ_64      0x00000040
#define    SZ_128     0x00000080
#define    SZ_256     0x00000100
#define    SZ_512     0x00000200
#define    SZ_1K      0x00000400
#define    SZ_2K      0x00000800
#define    SZ_4K      0x00001000
#define    SZ_8K      0x00002000
#define    SZ_16K     0x00004000
#define    SZ_32K     0x00008000
#define    SZ_64K     0x00010000
#define    SZ_128K    0x00020000
#define    SZ_256K    0x00040000
#define    SZ_512K    0x00080000
#define    SZ_1M      0x00100000
#define    SZ_2M      0x00200000
#define    SZ_4M      0x00400000
#define    SZ_8M      0x00800000
#define    SZ_16M     0x01000000
#define    SZ_32M     0x02000000
#define    SZ_64M     0x04000000
#define    SZ_128M    0x08000000
#define    SZ_256M    0x10000000
#define    SZ_512M    0x20000000
#define    SZ_1G      0x40000000
#define    SZ_2G      0x80000000

/***************
 * AAU Support *
 ***************/
/* Accelerator Control Register (ACR) */
#define I80312_ACR            0x1800
#define I80312_ACR_MASK       0x00000007
#define ACR_512B_ENABLE       0x00000003 /* set causes AAU to use only 512 bytes of the 1KB data buffer */
#define ACR_CHAIN_RESUME      0x00000002 /* set causes AAU to resume chaining by rereading ADAR when AAU is idle */
#define ACR_AAU_ENABLE        0x00000001 /* set causes AAU to enable transfers, */
#define ACR_AAU_DISABLE       0x00000000 /* clear disables any transfers */

/* Accelerator Status Register (ASR) */
#define I80312_ASR            0x1804
#define ASR_MASK              0x00000720
#define ASR_ACTIVE_FLAG       0x00000400 /* 1=ACTIVE, 0-IDLE */
#define ASR_ETI_FLAG          0x00000200 /* set when AAU signals an interrupt after processing descriptor in chain */
#define ASR_ECI_FLAG          0x00000100 /* set when channel signals an interrupt after processing last descriptor in chain */
#define ASR_MASTER_ABORT_FLAG 0x00000020 /* Master Abort during transaction when AAU master on internal bus */

/* Accelerator Descriptor Address Register (ADAR) */
#define I80312_ADAR           0x1808
#define I80312_ADAR_MASK      0xFFFFFFE0 /* aligned on an 8-word boundary, ignore bits 0-4 */

/* Accelerator Next Descriptor Address Register (AN1YDAR) */
#define I80312_ANDAR          0x180C
#define I80312_ANDAR_MASK     0xFFFFFFE0 /* aligned on an 8-word boundary, ignore bits 0-4 */

/* Processor Source Address Register (SAR) */
#define I80312_SAR1           0x1810
#define I80312_SAR2           0x1814
#define I80312_SAR3           0x1818
#define I80312_SAR4           0x181C
#define I80312_SAR5           0x182C
#define I80312_SAR6           0x1830
#define I80312_SAR7           0x1834
#define I80312_SAR8           0x1838

/* Processor Destination Address Register (DAR) */
#define I80312_DAR            0x1820

/* Accelerator Byte Count Register (ABCR) */
#define I80312_ABCR           0x1824
#define I80312_ABCR_MASK      0x00FFFFFF /* maximum XOR-transfer of 16Mbytes */

/* Accelerator Descriptor Control Register (ADCR) */
#define I80312_ADCR           0x1828
#define I80312_ADCR_MASK      0x87FFFFFF
#define ADCR_DES_WENABLE      0x80000000 /* Destination Write Enable, when set, data in Q written to DAR based on SARx */
#define ADCR_SBCI             0x06000000 /* Supplemental Block Control Interpreter, specifies number of data blocks on */
                                         /* which the XOR-transfer op executed. (0=0blocks, 1=4blocks, 2/3=RESERVED) */
#define ADCR_B8CC             0x01C00000 /* Block 8 Command Control, specifies type of op for SAR8, */
                                         /* 0=NULL, 1=XOR, 2-7=RESERVED */
#define ADCR_B7CC             0x00380000 /* Block 7 Command Control, specifies type of op for SAR7, */
                                         /* 0=NULL, 1=XOR, 2-7=RESERVED */
#define ADCR_B6CC             0x00070000 /* Block 6 Command Control, specifies type of op for SAR6, */
                                         /* 0=NULL, 1=XOR, 2-7=RESERVED */
#define ADCR_B5CC             0x0000E000 /* Block 5 Command Control, specifies type of op for SAR5, */
                                         /* 0=NULL, 1=XOR, 2-7=RESERVED */
#define ADCR_B4CC             0x00001C00 /* Block 4 Command Control, specifies type of op for SAR4, */
                                         /* 0=NULL, 1=XOR, 2-7=RESERVED */
#define ADCR_B3CC             0x00000380 /* Block 3 Command Control, specifies type of op for SAR3, */
                                         /* 0=NULL, 1=XOR, 2-7=RESERVED */
#define ADCR_B2CC             0x00000070 /* Block 2 Command Control, specifies type of op for SAR2, */
                                         /* 0=NULL, 1=XOR, 2-7=RESERVED */
#define ADCR_B1CC             0x0000000E /* Block 1 Command Control, specifies type of op for SAR1. */
                                         /* 0=NULL, 1=XOR, 2-6=RESERVED, 7=Direct Fill(-bypasses boolean execution unit) */
#define ADCR_INT_ENABLE       0x00000001 /* set: AAU generates interrupt upon completion of transfer, clear: no interrupt */

#ifdef __cplusplus
}
#endif

#endif  /* INCi80312h */