i80312.h

VXWORKS BSP开发包,初始化 驱动文件

/* i80312.h - Yavapai Companion Chip (I80312) header file */

/* Copyright 1984-1996 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,10jul02,scm  add C++ protection...
01f,15may01,jb  Adding register defs for limited fiq support
01e,19apr01,scm  added additional interrupt regs...
01d,26mar01,scm  add support for application accelerator unit...
01c,21mar01,scm  modify auto ram size params to better support multi-bank
                 SRAM...
01b,20nov00,scm  dimm auto sizing
01a,05sep00,scm  written.
*/

/*
DESCRIPTION
This file contains Yavapai register definitions
*/
#ifndef INCi80312h
#define INCi80312h

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE
#else
#endif

/*** Flash ***/
/* Register Addresses */
/* Use these defs for indexed addressing */
#define I80312_BASE		0x00001500 /* I80312 registers base address */
#define I80312_INDEX_SDIR	0x00	/* SDRAM Init Register Index */
#define I80312_INDEX_SDCR	0x04	/* SDRAM Control Register */
#define I80312_INDEX_SDBR	0x08	/* SDRAM Base Register */
#define I80312_INDEX_SBR0	0x0c	/* SDRAM Boandary Register 0 */
#define I80312_INDEX_SBR1	0x10	/* SDRAM Boandary Register 1 */
#define I80312_INDEX_SDPR0	0x14	/* SDRAM Page Register 0 */
#define I80312_INDEX_SDPR1	0x18	/* SDRAM Page Register 1 */
#define I80312_INDEX_SDPR2	0x1c	/* SDRAM Page Register 2 */
#define I80312_INDEX_SDPR3	0x20	/* SDRAM Page Register 3 */
#define I80312_INDEX_SDPR4	0x24	/* SDRAM Page Register 4 */
#define I80312_INDEX_SDPR5	0x28	/* SDRAM Page Register 5 */
#define I80312_INDEX_SDPR6	0x2c	/* SDRAM Page Register 6 */
#define I80312_INDEX_SDPR7	0x30	/* SDRAM Page Register 7 */
#define I80312_INDEX_ECCR 	0x34	/* ECC Control Register */
#define I80312_INDEX_ELOG0 	0x38	/* ECC Log Register 0 */
#define I80312_INDEX_ELOG1	0x3c	/* ECC Log Register 1 */
#define I80312_INDEX_ECAR0 	0x40	/* ECC Address Register 0 */
#define I80312_INDEX_ECAR1 	0x44	/* ECC Address Register 1 */
#define I80312_INDEX_ECTST 	0x48	/* ECC Test Register */
#define I80312_INDEX_FEBR0 	0x4c	/* Flash Bank Base Register 0 */
#define I80312_INDEX_FEBR1 	0x50	/* Flash Bank Base Register 1 */
#define I80312_INDEX_FBSR0 	0x54	/* Flash Bank Size Register 0 */
#define I80312_INDEX_FBSR1 	0x58	/* Flash Bank Size Register 1 */
#define I80312_INDEX_FWSR0 	0x5c	/* Flash Wait States Register 0 */
#define I80312_INDEX_FWSR1 	0x60	/* Flash Wait States Register 1 */
#define I80312_INDEX_MCISR 	0x64	/* Memory Controller Int Status Reg */
#define I80312_INDEX_RFR 	0x68	/* Refresh Frequency Register */

/* Use these defs for direct addressing */
#define I80312_SDIR	(I80312_BASE+0x00)	/* SDRAM Init Register Index */
#define I80312_SDCR	(I80312_BASE+0x04)	/* SDRAM Control Register */
#define I80312_SDBR	(I80312_BASE+0x08)	/* SDRAM Base Register */
#define I80312_SBR0	(I80312_BASE+0x0c)	/* SDRAM Boandary Register 0 */
#define I80312_SBR1	(I80312_BASE+0x10)	/* SDRAM Boandary Register 1 */
#define I80312_SDPR0	(I80312_BASE+0x14)	/* SDRAM Page Register 0 */
#define I80312_SDPR1	(I80312_BASE+0x18)	/* SDRAM Page Register 1 */
#define I80312_SDPR2	(I80312_BASE+0x1c)	/* SDRAM Page Register 2 */
#define I80312_SDPR3	(I80312_BASE+0x20)	/* SDRAM Page Register 3 */
#define I80312_SDPR4	(I80312_BASE+0x24)	/* SDRAM Page Register 4 */
#define I80312_SDPR5	(I80312_BASE+0x28)	/* SDRAM Page Register 5 */
#define I80312_SDPR6	(I80312_BASE+0x2c)	/* SDRAM Page Register 6 */
#define I80312_SDPR7	(I80312_BASE+0x30)	/* SDRAM Page Register 7 */
#define I80312_ECCR 	(I80312_BASE+0x34)	/* ECC Control Register */
#define I80312_ELOG0 	(I80312_BASE+0x38)	/* ECC Log Register 0 */
#define I80312_ELOG1	(I80312_BASE+0x3c)	/* ECC Log Register 1 */
#define I80312_ECAR0 	(I80312_BASE+0x40)	/* ECC Address Register 0 */
#define I80312_ECAR1 	(I80312_BASE+0x44)	/* ECC Address Register 1 */
#define I80312_ECTST 	(I80312_BASE+0x48)	/* ECC Test Register */
#define I80312_FEBR0 	(I80312_BASE+0x4c)	/* Flash Bank Base Register 0 */
#define I80312_FEBR1	(I80312_BASE+0x50) /* Flash Bank1 Base Reg */
#define I80312_FBSR0 	(I80312_BASE+0x54)	/* Flash Bank Size Register 0 */
#define I80312_FBSR1 	(I80312_BASE+0x58)	/* Flash Bank Size Register 1 */
#define I80312_FWSR0 	(I80312_BASE+0x5c)	/* Flash Wait States Register 0 */
#define I80312_FWSR1 	(I80312_BASE+0x60)	/* Flash Wait States Register 1 */
#define I80312_MCISR 	(I80312_BASE+0x64)	/* Memory Cntlr Int Status */
#define I80312_RFR 	(I80312_BASE+0x68)	/* Refresh Frequency Register */

#define I80312_BIUISR	0x00001644
#define BIUISR_ADDR	I80312_BIUISR	/* BIU interrupt status register */

/*** Interrupt ***/
#define I80312_X6ISR	(0x1708)	/* XINT6 Interrupt Status Register */
#define I80312_X7ISR	(0x1704)	/* XINT7 Interrupt Status Register */
#define I80312_PIRSR	(0x1050)
#define I80312_IIMR 	(0x1328)
#define I80312_OIMR 	(0x1334)
#define I80312_IISR     (0x1324)
#define I80312_CIUISR   (0x1644)

/*** DMA Registers ***/
#define I80312_DMACCR0  (0x1400)     
#define I80312_DMACSR0  (0x1404)

#define I80312_DMACCR1  (0x1440)     
#define I80312_DMACSR1  (0x1444)

#define I80312_DMACCR2  (0x1480)     
#define I80312_DMACSR2  (0x1484)

/* Refresh Cycles */
#define I80312_SDRAM_REFRESH_DISABLE	0x0	/* Diables Refresh Cycle */

/* SDRAM Commands 3 LSBs */
#define I80312_SDRAM_CMD_MRS0	0x0	/* Mode Reg Set Cmd CAS Latency 2 */
#define I80312_SDRAM_CMD_MRS1	0x1	/* Mode Reg Set Cmd CAS Latency 3 */
#define I80312_SDRAM_CMD_PCA	0x2	/* PrechargeAll Command */
#define I80312_SDRAM_CMD_NOP	0x3	/* NOP Command to SDRAM devices */
#define I80312_SDRAM_CMD_AR	0x4	/* Auto refresh Command */
#define I80312_SDRAM_CMD_OPER	0x6	/* >= 6 <= 7 Normal SDRAM operation */

#define SDCR_ADDR 0x00001504            /* Address of the Refresh Counter */

#define         ECC_CORR_REP_ENABLE     0x7     /* Yavapai enable ECC correction and reporting */
#define         ECC_CORR_ENABLE         0x4     /* Yavapai enable ECC correction disable reporting */

/* Valid Size definitions */
#define I80312_FLASH_SIZE_ZERO	  0x00000000 /* size 0 disables flash bank */
#define I80312_FLASH_SIZE_64K	  0x00000001 /* 1 - 64K */
#define I80312_FLASH_SIZE_128K	  0x00000002 /* 2 - 128K */
#define I80312_FLASH_SIZE_256K	  0x00000003 /* 3 - 256K */
#define I80312_FLASH_SIZE_512K	  0x00000004 /* 4 - 512K */
#define I80312_FLASH_SIZE_1MEG	  0x00000005 /* 5 - 1Meg */
#define I80312_FLASH_SIZE_2MEG	  0x00000006 /* 6 - 2Meg */
#define I80312_FLASH_SIZE_4MEG	  0x00000007 /* 7 - 4Meg */
#define I80312_FLASH_SIZE_8MEG	  0x00000008 /* >= 8 - 8Meg */
#define I80312_FLASH_DISABLE      I80312_FLASH_SIZE_ZERO /* disable flash */

/**************************
 * I2C Bus Interface Unit *
 **************************/
/* Control Register */
#define ICR_ADDR       0x00001680  /* Address */
#define ICR_START      0x0001      /* 1:send a Start condition to the I2C when in master mode */
#define ICR_STOP       0x0002      /* 1:send a Stop condition after next data byte transferred on I2C bus in master mode */
#define ICR_ACK        0x0004      /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
#define ICR_TRANSFER   0x0008      /* 1:send/receive byte, 0:cleared by I2C unit when done */
#define ICR_ABORT      0x0010      /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
#define ICR_SCLENB     0x0020      /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
#define ICR_ENB        0x0040      /* I2C unit: 1:Enabled, 0:Disabled */
#define ICR_GCALL      0x0080      /* General Call: 1:Disabled, 0:Enabled */
#define ICR_IEMPTY     0x0100      /* 1: IDBR Transmit Empty Interrupt Enable */
#define ICR_IFULL      0x0200      /* 1: IDBR Receive Full Interrupt Enable */
#define ICR_IERR       0x0400      /* 1: Bus Error Interrupt Enable */
#define ICR_ISTOP      0x0800      /* 1: Slave Stop Detected Interrupt Enable */
#define ICR_IARB       0x1000      /* 1: Arbitration Loss Detected Interrupt Enable */
#define ICR_ISADDR     0x2000      /* 1: Slave Address Detected Interrupt Enable */
#define ICR_RESET      0x4000      /* 1: I2C unit reset */

/* Status Register */
#define ISR_ADDR       0x00001684  /* Address */
#define ISR_RWMODE     0x0001      /* 1: I2C in master receive = slave transmit mode */
#define ISR_ACK        0x0002      /* 1: I2C received/sent a Nack, 0: Ack */
#define ISR_BUSY       0x0004      /* 1: Processor's I2C unit busy */
#define ISR_BUSBUSY    0x0008      /* 1: I2C bus busy. Processor's I2C unit not involved */
#define ISR_STOP       0x0010      /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
#define ISR_ARB        0x0020      /* 1: Arbitration Loss Detected */
#define ISR_EMPTY      0x0040      /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
#define ISR_FULL       0x0080      /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */