iq80310.h

VXWORKS BSP开发包,初始化 驱动文件

/* iq80310.h - header for IQ80310 eval board */

/* Copyright 2000 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,10jul02,scm  add C++ protection...
01f,18jan02,scm  update #include's
01e,11may01,scm  update rotary switch...
01d,17apr01,scm  added support to identify extended interrupts...
01c,21mar01,scm  modify initial SDRAM params...
01b,12feb01,scm  add vars for data cache lock mode
01a,05sep00,scm  written
*/

/*
DESCRIPTION
This file contains I/O address and related constants for the IQ80310 Eval
board.
*/
#ifndef INCiq80310h
#define INCiq80310h

#ifdef __cplusplus
extern "C" {
#endif

/* Data Cache Lock Register Modes */
#define  IQ80310_DATA_CACHE_NO_LOCKING  0x0  /* No locking occurs */
#define  IQ80310_DATA_CACHE_LOCKED      0x1  /* any fill into the data cache while this */
                                             /* bit is set gets locked in               */

/** UART related defs. There are two UARTS in IQ80310 Eval Board **/
#define IQ80310_UART_BASE_UART1 0xfe800000	/* UART 1 base address */

#ifdef SECOND_HEX_LED
#define IQ80310_UART_BASE_UART2 0xfe810000	/* UART 2 base address */
#endif

#define IQ80310_UART_XTAL       1843200 /* UART Clock frequency (for both) */
#define IQ80310_UART_REG_DELTA  1	/* Byte space between registers */
#define IQ80310_UART_N_UARTS	2	/* Two UARTs in this board */

/* Receive Holding Reg. */
#define I80310_UART1_REC_HOL_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1))
/* Interrupt Enable Reg. */
#define I80310_UART1_INT_ENB_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1 + 1))
/* Interrupt Status Reg. */
#define I80310_UART1_INT_STT_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1 + 2))
/* Line Control Reg. */
#define I80310_UART1_LN_CTRL_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1 + 3))
/* Modem Control Reg. */
#define I80310_UART1_MD_CTRL_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1 + 4))
/* Line Status Reg. */
#define I80310_UART1_LN_STAT_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1 + 5))
/* Modem Status Reg. */
#define I80310_UART1_MD_STAT_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1 + 6))
/* Scratch Pad Reg. */
#define I80310_UART1_SCR_PAD_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART1 + 7))

/* Transmit Holding Reg. */
#define I80310_UART1_TX_HOL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART1) = (UINT8)mask
/* Interrupt Enable Reg. */
#define I80310_UART1_INT_ENB_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART1 + 1) = (UINT8)mask
/* FIFO Control Reg. */
#define I80310_UART1_FIFO_CTRL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART1 + 2) = (UINT8)mask
/* Line Control Reg. */
#define I80310_UART1_LN_CTRL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART1 + 3) = (UINT8)mask
/* Modem Control Reg. */
#define I80310_UART1_MD_CTRL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART1 + 4) = (UINT8)mask
/* Scratch Pad Reg. */
#define I80310_UART1_SCR_PAD_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART1 + 7) = (UINT8)mask

#ifdef SECOND_HEX_LED
#define I80310_UART2_REC_HOL_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2))
#define I80310_UART2_INT_ENB_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2 + 1))
#define I80310_UART2_INT_STT_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2 + 2))
#define I80310_UART2_LN_CTRL_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2 + 3))
#define I80310_UART2_MD_CTRL_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2 + 4))
#define I80310_UART2_LN_STAT_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2 + 5))
#define I80310_UART2_MD_STAT_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2 + 6))
#define I80310_UART2_SCR_PAD_REG_RD()\
        (*(volatile UINT8*)(IQ80310_UART_BASE_UART2 + 7))

#define I80310_UART2_TX_HOL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART2) = (UINT8)mask
#define I80310_UART2_INT_ENB_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART2 + 1) = (UINT8)mask
#define I80310_UART2_FIFO_CTRL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART2 + 2) = (UINT8)mask
#define I80310_UART2_LN_CTRL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART2 + 3) = (UINT8)mask
#define I80310_UART2_MD_CTRL_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART2 + 4) = (UINT8)mask
#define I80310_UART2_SCR_PAD_REG_WR(mask)\
        *(UINT8*)(IQ80310_UART_BASE_UART2 + 7) = (UINT8)mask
#endif

/** Board Revision */ 
#define IQ80310_BOARD_REVISION 0xfe830000 /* Board Revision Reg., BIT0-BIT3=2h >>REV. B */

#define I80310_BRD_REV_REG_RD()\
        (*(volatile UINT8*)(IQ80310_BOARD_REVISION))

/* CPLD Revision */
#define IQ80310_CPLD_REVISION 0xfe840000 /* CPLD Revision Reg., BIT0-BIT3=2h >>REV. B */

#define I80310_CPLD_REV_REG_RD()\
        (*(volatile UINT8*)(IQ80310_CPLD_REVISION))

/** 7 Segment LCDs  MSB/LSB **/
/** 0-On, 1-Off **/
/*
          A1/2
          Bit 0                    
        ---------
       |        |
 F1/2  |        | B1/2
 Bit 5 |        | Bit 1
       | G1/2   |
       | Bit 6  |
        ---------
       |        |
 E1/2  |        | C1/2
 Bit 4 |        | Bit 2
       | D1/2   |
       | Bit 3  |       DP1/2
        ---------     * Bit 7 (dot)
*/

/** Numerals **/
#define L7SEG_0         0xC0    /* 0 */
#define L7SEG_1         0xF9    /* 1 */
#define L7SEG_2         0xA4    /* 2 */
#define L7SEG_3         0xB0    /* 3 */
#define L7SEG_4         0x99    /* 4 */
#define L7SEG_5         0x92    /* 5 */
#define L7SEG_6         0x82    /* 6 */
#define L7SEG_7         0xF8    /* 7 */
#define L7SEG_8         0x80    /* 8 */
#define L7SEG_9         0x98    /* 9 */

/** Alphas **/
#define L7SEG_A         0x88    /* A */
#define L7SEG_B         0x83    /* b */
#define L7SEG_C         0xC6    /* C */
#define L7SEG_D         0xA1    /* D */
#define L7SEG_E         0x86    /* E */
#define L7SEG_F         0x8E    /* F */
#define L7SEG_g         0x90    /* g */
#define L7SEG_H         0x89    /* H */
#define L7SEG_h         0x8B    /* h */
#define L7SEG_i         0xFB    /* i */
#define L7SEG_J         0xE1    /* J */
#define L7SEG_L         0xC7    /* L */
#define L7SEG_n         0xAB    /* n */
#define L7SEG_o         0x9C    /* o */
#define L7SEG_P         0x8C    /* P */
#define L7SEG_r         0x8F    /* r */
#define L7SEG_S         0x92    /* S */
#define L7SEG_U         0xC1    /* U */
#define L7SEG_u         0xE3    /* u */

/** Segment On **/
#define L7SEG_Tp        0xFE    /* top */
#define L7SEG_Tr        0xFD    /* top right */
#define L7SEG_Br        0xFB    /* bottom right */
#define L7SEG_Rs        0xF9    /* right side */
#define L7SEG_Bm        0xF7    /* bottom */
#define L7SEG_Bl        0xEF    /* bootom left */
#define L7SEG_Tl        0xDF    /* top left */
#define L7SEG_Ls        0xCF    /* left side */
#define L7SEG_Md        0xBF    /* middle */
#define L7SEG_Dot       0x7F    /* dot */

#define L7SEG_ALL_ON    0x00    /* 8.*/
#define L7SEG_ALL_OFF   0xFF    /*   */

#ifdef SECOND_HEX_LED
#define IQ80310_7SEG_BASE_MSB 0xfe840000 /* 7 Segment MSB base address */

#define IQ80310_SEVEN_SEG_WRITE_MSB(value)\
                                  *(UINT8*)(IQ80310_7SEG_BASE_MSB)=value
#endif

#define IQ80310_7SEG_BASE_LSB 0xfe850000 /* 7 Segment LSB base address */

#define IQ80310_SEVEN_SEG_WRITE_LSB(value)\
                                  *(UINT8*)(IQ80310_7SEG_BASE_LSB)=value

/** Timer **/
/* this timer has 4-8bit counter */
#define IQ80310_TIMER_LA0          0xfe880000 /* Counter bits 7-0 */
#define IQ80310_TIMER_LA1          0xfe890000 /* Counter bits 15-8 */
#define IQ80310_TIMER_LA2          0xfe8a0000 /* Counter bits 23-16 */
#define IQ80310_TIMER_LA3          0xfe8b0000 /* Counter bits 31-24 */
#define IQ80310_TIMER_CR           0xfe8c0000 /* Timer Control */

#define IQ80310_TIMER_INT_ACK	   0x01       /* ack timer int */
#define IQ80310_TIMER_MASK_ENABLE  0x03       /* Enable Timer */
#define IQ80310_TIMER_MASK_DISABLE 0x00       /* Disable Timer */

#define SYS_CLK_RATE_MIN          0xA     /* Minimum rate at which the system clock can run */
#define SYS_CLK_RATE_MAX          0x258   /* 600 ticks, Maximum rate at which the system clock can run */

                                          /* Do not actually have an auxiliary clock */
#define AUX_CLK_RATE_MIN          0xA     /* Minimum rate at which the auxiliary clock can run */
#define AUX_CLK_RATE_MAX          0x258   /* 600 ticks, Maximum rate at which the auxiliary clock can run */

/* Also NOTE: The current system has no suitable spare timers, thus requiring  */
/*            that timestamps be derived from vxWorks system clock timer.      */

/* Timer Reload Register 0 thru 3 */
#define EP310_TRR0 ((unsigned long *) IQ80310_TIMER_LA0)
#define EP310_TRR1 ((unsigned long *) IQ80310_TIMER_LA1)
#define EP310_TRR2 ((unsigned long *) IQ80310_TIMER_LA2)
#define EP310_TRR3 ((unsigned long *) IQ80310_TIMER_LA3)

/* Timer Control Register  */
#define EP310_TCR0 ((unsigned long *) IQ80310_TIMER_CR)

/** Rotary switch **/
#define IQ80310_RS_STATUS        0xfe8d0000 /* Rotary switch position read */
#define IQ80310_RS_MASK_SIGNAL_A 0x01       /* Singnal A selected */
#define IQ80310_RS_MASK_SIGNAL_B 0x02       /* Singnal B selected */
#define IQ80310_RS_MASK_SIGNAL_C 0x04       /* Singnal C selected */
#define IQ80310_RS_MASK_SIGNAL_D 0x08       /* Singnal D selected */

#define I80310_ROT_STAT_REG_RD()\
        ((*(volatile UINT8*)(IQ80310_RS_STATUS)) & 0x0F)

/** JTAG **/
/* JTAG Port address 0xfe8e0000 through 0xfe8e0078 A6:A3 significant only */
#define IQ80310_JTAG_PORT 0xfe8e0000 /* JTAG Port address */

/* Battery */
#define IQ80310_BATTERY_STATUS       0xfe8f0000 /* Battery Status read */
#define IQ80310_BATTERY_MASK_PRES    0x01       /* Battery Present */
#define IQ80310_BATTERY_MASK_CHRG    0x02       /* Battery Charged */
#define IQ80310_BATTERY_MASK_DISCHRG 0x04       /* Battery Discharged */

#define I80310_BAT_STAT_REG_RD()\
        (*(volatile UINT8*)(IQ80310_BATTERY_STATUS))

/** Interrupts **/
/*
 * Interrupt can Masked and deducted at PAL level. When reading
 * IQ80310_PAL_INT_STATUS_MASK, bit set indicates that interrupt has
 * occured. Interrupts can be masked by settting bits at
 * IQ80310_PAL_INT_STATUS_MASK
 */
#define IQ80310_PAL_INT_STATUS        0xfe820000 /* PAL INTs Status */
#define IQ80310_PAL_INT_STATUS_MASK   0xfe860000 /* PAL INTs Mask/Status */
#define IQ80310_PAL_INT_MASK_TIMER    0x01       /* timer interrupt */
#define IQ80310_PAL_INT_MASK_ETHERNET 0x02       /* Ethernet interrupt */
#define IQ80310_PAL_INT_MASK_UART1    0x04       /* UART1 interrupt */
#define IQ80310_PAL_INT_MASK_UART2    0x08       /* UART2 interrupt */
#define IQ80310_PAL_INT_MASK_SPCID    0x10       /* Seconday PCI INT_D */

#define I80310_PAL_XINT3_INT_MASK_WR(mask)\
        *(UINT8*)(IQ80310_PAL_INT_STATUS_MASK) = (UINT8)mask

#define I80310_PAL_XINT3_INT_MSK_RD()\
        (*(volatile UINT8*)(IQ80310_PAL_INT_STATUS_MASK))

#define I80310_PAL_XINT3_INT_ISR_RD()\
        (*(volatile UINT8*)(IQ80310_PAL_INT_STATUS))

/* on Rev-F boards or better, we can see if INT_A, INT_B, or INT_C occurred */
#define IQ80310_PAL_SINT_MASK         0x7        /* isolate bits b0-b2 */
#define IQ80310_PAL_INT_MASK_SPCIA    0x01       /* Seconday PCI INT_A */
#define IQ80310_PAL_INT_MASK_SPCIB    0x02       /* Seconday PCI INT_B */
#define IQ80310_PAL_INT_MASK_SPCIC    0x04       /* Seconday PCI INT_C */

#define I80310_PAL_XINT3_EXTND_INT_ISR_RD()\
        (*(volatile UINT8*)(IQ80310_7SEG_BASE_LSB))

/** Backplane **/
#define IQ80310_BACKPLANE_STATUS        0xfe870000 /* Backplane status */
#define IQ80310_BACKPLANE_MASK_DETECTED 0x01       /* Backplane detected */

#define I80310_BACKPLANE_STAT_RD()\
        (*(volatile UINT8*)(IQ80310_BACKPLANE_STATUS))

/* This currently does not work for all PCs */
#define I80310_BACKPLANE_DETECT()\
        (IQ80310_BACKPLANE_MASK_DETECTED & (*(volatile UINT8*)(IQ80310_BACKPLANE_STATUS)))

/** Flash ROMs Defaults **/
/* By default Flash Bank 0 is disabled (FBSR0 contains 0x00000000) */
#define IQ80310_FLASH_BANK0_BASE	0xfe800000 /* Flash Bank0 Base */
#define IQ80310_FLASH_BANK0_SIZE	0x00100000 /* 1 Meg */

#define IQ80310_FLASH_BANK1_BASE	0x00000000 /* Flash Bank1 Base */
#define IQ80310_FLASH_BANK1_SIZE	0x00800000 /* 8 Meg */

/*** SDRAM ***/
/* DRAM Starting Address */
#define IQ80310_SDRAM_BASE_ADRS		0xa0000000 /* DRAM Address */

/* Initial Size for Bank 0 and Bank 1. Take bits 7-3 and Multiply by 32Meg */
#define IQ80310_SDRAM_SBR0_INIT_VAL     0x8     /* 32Megs in bank zero */
#define IQ80310_SDRAM_SBR1_INIT_VAL     0x8     /* Unpopulated bank one */

#define IQ80310_SDRAM_ECC_INIT_VAL       0x0C   /* ECC enabled, correction on and no reporting */

/* Should be generate at least 200 microSec delay in a assembly spin loop */
#define IQ80310_SDRAM_NOP_DELAY_CNT	0x00004000  /* Delay Count */

/* Initial SDRAM Refresh Rate */
#define IQ80310_SDRAM_RFR_INIT_VAL	0x00000600  /* Refresh rate */

/* Assembly specific defs */
#ifndef _ASMLANGUAGE
#endif

#ifdef __cplusplus
}
#endif

#endif  /* INCiq80310h */