📄 rominit.s
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strb r0, [r10, #UART_FIFOControl] /* turn fifos on */ mov r0, #UARTFCR_RXReset | ARTFCR_TXReset | UARTFCR_Mode0RXRDYTXRDY | UARTFCR_RXTrigger1 strb r0, [r10, #UART_FIFOControl] /* make DTR active, RTS inactive, stop other end */ mov r0, #UARTMCR_DTRActive strb r0, [r10, #UART_ModemControl] mov pc, lr/************************** Print Helpers ******************************************/PrintString:110: ldrb r0, [lr], #1/* the following chunk enables LF to CR+LF translation */ teq r0, #0x0A /* LF (linefeed?) */ bne 120f mov r0, #0x0D /* CR */11: ldr r1, =SERIAL_DISPLAY ldrb r2, [r1, #UART_LineStatus] tst r2, #UARTLSR_TXHoldingEmpty beq 11b strb r0, [r1, #UART_Transmit] mov r0, #0x0A /* LF */120: teq r0, #0 /* test for the string termination character (0) */ beq 130f12: ldrb r2, [r1, #UART_LineStatus] tst r2, #UARTLSR_TXHoldingEmpty beq 12b strb r0, [r1, #UART_Transmit] b 110b130: add lr, r14, #3 /* round up to next word boundary */ bic pc, r14, #3/* * Print 32-bit hex value subroutine * in: r0 = value to print in hex */PrintHex32: mov r2, r14 mov r1, r0, LSR #28 bl PrintHexDigit mov r1, r0, LSR #24 bl PrintHexDigit mov r1, r0, LSR #20 bl PrintHexDigit mov r1, r0, LSR #16 bl PrintHexDigit mov r1, r0, LSR #12 bl PrintHexDigit mov r1, r0, LSR #04 mov r1, r1, LSR #04 bl PrintHexDigit mov r1, r0, LSR #04 bl PrintHexDigit mov r1, r0 bl PrintHexDigit mov pc, r2PrintHexDigit: and r1, r1, #0x0F cmp r1, #10 addcc r1, r1, #'0' addcs r1, r1, #'A'-10 ldr r3, =SERIAL_DISPLAY13: ldrb r4, [r3, #UART_LineStatus] tst r4, #UARTLSR_TXHoldingEmpty beq 13b strb r1, [r3, #UART_Transmit] mov pc, r14/************************** AUTO Size Mem *****************************************/SIZEDimm:/******* I2C interface initialization ****************************************/ /* Setup I2C Slave Address Register */ ldr r1, =I2C_DEVID /* Load slave address r1.*/ ldr r2, =ISAR_ADDR /* Load address of the I2C Slave Address Register in r2. */ ldr r3, =0x0000007f /* Load mask in r3. */ and r1, r3, r3 /* The mask zeroes the 25 MSBs of r1 just to make sure. */ str r3, [r2] /* Save the value 0x02 (I2C_DEVID) in the register. */ /* Setup I2C Clock Count Register */ ldr r2, =ICCR_ADDR /* Load the address of the I2C Clock Control Register in r2. */ ldr r3, =0x0000014d /* Set for 5.05 us transition time at 66MHz (0x14D = 333). */ str r3, [r2] /* Save the value in the register. */ /* Enable I2C Interface Unit - status will be polled */ ldr r2, =ICR_ADDR /* Load the address of the Control Register in r2. */ ldr r1, =ICR_GCALL /* Disable General Call (will be master) */ ldr r3, =ICR_ENB /* Enable I2C unit ). */ orr r1, r3, r1 /* OR the two and store in R1 */ ldr r3, =ICR_SCLENB /* Enable I2C Clock Generator disabled */ orr r1, r3, r1 /* OR the two and store in R1 */ str r1, [r2] /* Save the value to the Control Register. *//****** Now read the SPD Data *************************************************/ /* Pointers to I2C Registers */ ldr r11, =ICR_ADDR /* Load the address of the I2C Control Register in r11. */ ldr r12, =ISR_ADDR /* Load the address of the I2C Status Register in r12. */ ldr r13, =IDBR_ADDR /* Load the address of the I2C Data Buffer Register in r13. */ /* Initialize byte counters */ ldr r5, =0x00000000 /* R5 has running checksum calculation */ ldr r7, =0x00000000 /* Counter incremented before byte is read */ ldr r9, =I2C_TIMOUT /* Timeout limit in case EEPROM does not respond */ /* At the end of all this, R4 has DRAM size, R8 has bank count, and R10 has Bank size */ ldr r10,=0x00000000 /* Bank size */ ldr r6, =0x00000000 /* Bank count */ ldr r4, =0x00000000 /* SDRAM size */ /* FREE REGISTERS ARE R0 - R3 *//*** Put out address, with WRITE mode ***/ /* Set SDRAM module address and write mode */ ldr r1, =SDRAM_DEVID /* Load slave address for SDRAM module: 0xA2 (Presence Detect Data) */ bic r1, r1, #IDBR_MODE /* Clear read bit (bit #0) */ str r1, [r13] /* Store to data register */ /* Initiate dummy write to set EEPROM pointer to 0 */ ldr r1, [r11] /* read the current Control Register value */ orr r1, r1, #ICR_START /* Set start bit */ orr r1, r1, #ICR_TRANSFER /* Set transfer bit - bit is self_clearing */ str r1, [r11] /* Store to control register */ /* Wait for transmit empty status */ ldr r1, =0x00000000 /* Initialize I2C timeout counter */0: add r1, r1, #1 /* Increment I2C timeout counter (r1 = r1 + 1) */ cmp r1, r9 beq i2c_error /* Kick out of SDRAM initialization if timeout occurs */ ldr r0, [r12] /* Load I2C Status Reg into R0 */ ldr r2, =ISR_EMPTY /* Poll status register */ and r3, r2, r0 /* Bit #6 is checked: IDBR Transmit Empty */ cmp r3, r2 /* If bit = 0 then branch to 0 and check again */ bne 0b str r0, [r12] /* Write back status to clear *//*** Write pointer register on EEPROM to 0x00000000 ***/ /* Set SDRAM module EEPROM address to 0 */ ldr r1, =0x00000000 /* Load base address of SDRAM module EEPROM */ str r1, [r13] /* Store to data register */ /* Send address to EEPROM */ ldr r1, [r11] /* read the current Control Register value */ bic r1, r1, #ICR_START /* No start bit (already started) */ orr r1, r1, #ICR_TRANSFER /* Set transfer bit - bit is self_clearing */ str r1, [r11] /* Store to control register */ /* Wait for transmit empty status */ ldr r1, =0x00000000 /* Initialize I2C timeout counter */0: add r1, r1, #1 /* Increment I2C timeout counter (r1 = r1 + 1) */ cmp r1, r9 beq i2c_error /* Kick out of SDRAM initialization if timeout occurs */ ldr r0, [r12] /* Load I2C Status Reg into R0 - ld (r12), r10*/ ldr r2, =ISR_EMPTY /* Poll status register */ and r3, r2, r0 /* Bit #6 is checked: IDBR Transmit Empty */ cmp r3, r2 /* If bit = 0 then branch to 0 and check again (r3 = 0x00)*/ bne 0b str r0, [r12] /* Write back status to clear *//******* Read SDRAM PD data ************************************************//*** Put out address, with READ mode ***/ /* Set SDRAM module address and read mode */ ldr r0, =SDRAM_DEVID /* Load slave address for SDRAM module (0xA2) */ orr r1, r0, #IDBR_MODE /* Set read bit (bit #0) */ str r1, [r13] /* Store to data register */ /* Send next read request */ ldr r1, [r11] /* read the current Control Register value */ orr r1, r1, #ICR_START /* Set start bit */ orr r1, r1, #ICR_TRANSFER /* Set transfer bit - bit is self_clearing */ str r1, [r11] /* Store to control register */ /* Wait for transmit empty status */ ldr r1, =0x00000000 /* Initialize I2C timeout counter */0: add r1, r1, #1 /* Increment I2C timeout counter (r1 = r1 + 1) */ cmp r1, r9 beq i2c_error /* Kick out of SDRAM initialization if timeout occurs */ ldr r0, [r12] /* Load I2C Status Reg into R0 - ld (r12), r10*/ ldr r2, =ISR_EMPTY /* Poll status register */ and r3, r2, r0 /* Bit #6 is checked: IDBR Transmit Empty */ cmp r3, r2 /* If bit = 0 then branch to 0 and check again (r3 = 0x00)*/ bne 0b str r0, [r12] /* Write back status to clear */sdram_loop: add r7, r7, #1 /* Increment byte counter *//*** READ the next Byte!!! ***/ ldr r1, [r11] /* read the current Control Register value */ bic r1, r1, #ICR_START /* No start bit (already started) */ orr r1, r1, #ICR_TRANSFER /* Set transfer bit - bit is self_clearing */ /* we have to set NACK before reading the last bit */ /* Number of bytes to read in the Presence Detect EEPROM of SDRAM: 64 bytes */ cmp r7, #0x00000040 /* 64 (decimal) so if r7 = 64, this is the last byte to be read */ bne 1f /* If bytes left, skip ahead */ orr r1, r1, #ICR_ACK /* Set NACK if this is the last byte */ orr r1, r1, #ICR_STOP /* Set STOP if this is the last byte */1: str r1, [r11] /* Store to control register */ /* Wait for read full status */ ldr r1, =0x00000000 /* Initialize I2C timeout counter */0: add r1, r1, #1 /* Increment I2C timeout counter (r1 = r1 + 1) */ cmp r1, r9 beq i2c_error /* Kick out of SDRAM initialization if timeout occurs */ ldr r0, [r12] /* Load I2C Status Reg into R0 */ ldr r2, =ISR_FULL /* Poll status register */ and r3, r2, r0 /* Bit #6 is checked: IDBR Transmit Empty */ cmp r3, r2 /* If bit = 0 then branch to 0 and check again */ bne 0b str r0, [r12] /* Write back status to clear */ /* Read the data byte */ ldr r1, [r13] /* Read the byte */ ldr r2, =CHECKSUM_BYTE cmp r7, r2 /* is it the CHECKSUM byte??? */ beq 1f add r5, r5, r1 /* Add it to the checksum if not the checksum byte */ bal 2f /* skip checksum comparison */1: ldr r0, =0xff /* If this is the checksum byte, compare it */ and r5, r5, r0 /* against the calculated checksum */ cmp r1, r5 bne bad_checksum /* If no match, skip SDRAM controller initialization */2: ldr r2, =BANKCNT_BYTE /* Check for bank count byte */ cmp r7, r2 bne 1f mov r6, r1 /* Store bank count */1: ldr r2, =BANKSZ_BYTE /* Check for bank size byte */ cmp r7, r2 bne 1f ldr r2, =0x04 /* Store bank size in Mbytes (shift left 2 bits) */ mul r10, r1, r2 mul r2, r6, r10 /* Multiply by bank count to get DRAM size in MB */ ldr r0, =0x100000 mul r4, r2, r0 /* Convert size to bytes - r4 contains DRAM size in bytes */1:/* Handle the SDRAM drive strength setup here since we are out of * temporary registers to hold the SDRAM width value until after * all of the SPD data has been read. Using the value of r8 for * the Bank Count is allright here since the SPD specification states that * the Bank Count SPD byte is #5 and the SDRAM Width SPD byte is #13. */ ldr r2, =SDRAM_WIDTH_BYTE /* Check for SDRAM width byte */ cmp r7, r2 bne 1f ldr r2, =0x10 /* Check for data width of 16 */ cmp r1, r2 bne SDRAM_DRIVE_X8 /* Module is composed of x16 devices */ ldr r2, =0x02 cmp r2, r6 /* do we have 2 banks??? */ beq SDRAM_DRIVE_2_BANK_X16 /* Module is composed of 1 Bank of x16 devices */ ldr r1, =SDCR_ADDR /* point at SDRAM Control Register */ ldr r2, =SDCR_1BANK_X16 /* drive strength value */ str r2, [r1] /* set value in SDCR */ b 1fSDRAM_DRIVE_2_BANK_X16: /* Module is composed of 2 Banks of x16 devices */ ldr r1, =SDCR_ADDR /* point at SDRAM Control Register */ ldr r2, =SDCR_2BANK_X16 /* drive strength value */ str r2, [r1] /* set value in SDCR */ b 1fSDRAM_DRIVE_X8: /* Module is composed of x8 devices */ ldr r2, =0x02 cmp r2, r6 /* do we have 2 banks??? */ beq SDRAM_DRIVE_2_BANK_X8 /* Module is composed of 1 Bank of x8 devices */ ldr r1, =SDCR_ADDR /* point at SDRAM Control Register */ ldr r2, =SDCR_1BANK_X8 /* drive strength value */ str r2, [r1] /* set value in SDCR */ b 1fSDRAM_DRIVE_2_BANK_X8: /* Module is composed of 2 Banks of x16 devices */ ldr r1, =SDCR_ADDR /* point at SDRAM Control Register */ ldr r2, =SDCR_2BANK_X8 /* drive strength value */ str r2, [r1] /* set value in SDCR */1: /* Continue reading bytes if not done */ cmp r7, #0x00000040 bne sdram_loop b i2c_disablebad_checksum: mov r0, #L7SEG_B mov r1, #L7SEG_C bl SevenSegDisplay b bad_checksumi2c_error: /* hit the leds if an error occurred */#ifdef SECOND_HEX_LED mov r0, #L7SEG_1 & L7SEG_Dot#endif mov r1, #L7SEG_C & L7SEG_Dot bl SevenSegDisplay b i2c_errori2c_disable: /* Disable I2C Interface Unit */ ldr r1, [r11] bic r1, r1, #ICR_ENB /* Disable I2C unit */ bic r1, r1, #ICR_SCLENB /* Disable I2C clock generator */ str r1, [r11] /* Store to control register */ mov pc, lrL$StrtInRam: .long ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)L$STACK_ADDR: .long STACK_ADRS⌨️ 快捷键说明
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