rominit.s

VXWORKS BSP开发包,初始化 驱动文件

/* any data added here should reflect in ROM_TEXT_BASE in Makefile as well as in config.h */

        .text
        .align 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* This is the start of the ROM code.  The CPU will vector here upon reset.
*
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
*
* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*
* Register r8 holds startType until jump to the code that starts the whole
* vxWorks boot process
*
*/

_ARM_FUNCTION(romInit)
_romInit:
cold:
        MOV     r0, #BOOT_COLD   /* fall through to warm boot entry */

warm:
        B       bootStart

        /* copyright notice appears at beginning of ROM (in TEXT segment) */
        .ascii  "Copyright 2000 Wind River Systems, Inc. "
        .align 4

bootStart:
        MOV     r8, r0           /* store off startType */

/*** Disable Write Buffer Coalescing ***/
	mcr		p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
	CPWAIT(r0)						/* wait for the write to happen */
	CPWAIT(r0)						/* wait for the write to happen */

	mrc		p15, 0, r0, c1, c0, 1   /* Read Auxiliary Control Reg */
	orr		r0, r0, #0x00000001     /* Disable Coalescing */
	mcr		p15, 0, r0, c1, c0, 1   /* Write Auxiliary Control Reg */
	CPWAIT(r0)						/* wait for the write to happen */

	ldr		r2, =0x1042
	ldr		r3, =0x3FF
	strh		r3, [r2]

	ldr		r2, =0x1040		/* quit PCI retries */
	mov		r3, #0x08
	strh		r3, [r2]

/* Delay appx 2 ms to let battery-backup reset complete */
	DELAY(0x20000, r0)

/* Enable Coprocessors CP0 and  CP13 access */
        ldr     r0, =0x2001
        mcr     p15, 0, r0, c15, c1, 0

        mcr     p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
        CPWAIT(r0)                      /* wait for the write to happen */

/* Disable Interrupts */
        MRS     r1, cpsr                /* get current status */
        ORR     r1, r1, #I_BIT | F_BIT  /* disable IRQ and FIQ */
        MSR     cpsr, r1

        mov     r0, #0                  /* Disable IRQ and FIQ Masks */
        mcr     p13, 0, r0, c0, c0, 0
/* Interrupts Disabled */

/* Invalidate I-Cache, D-Cache, and BTB */
        mcr     p15, 0, r0, c7, c7, 0
        CPWAIT(r0)                      /* Wait */

/* Drain Write/Fill buffer.  */
        mcr     p15, 0, r0, c7, c10, 4
        CPWAIT  (r0)

/* fall through to warm boot entry */
        cmp     r8, #BOOT_COLD
        bne     warm_start

/* End of BUS0, First Access to & Segment */
#ifdef SECOND_HEX_LED
	mov		r0, #L7SEG_S & L7SEG_Dot
#endif
	mov		r1, #L7SEG_0 & L7SEG_Dot
	bl		SevenSegDisplay

/*establish UART for debug... */
        bl              UARTStart

        bl      PrintString
        .ascii  "\n"
        .ascii  "==============================\n"
        .ascii  "= UART Up and Initialized... =\n"
        .ascii  "==============================\n\0"
        .align 2

/* End of BUS1 */
#ifdef SECOND_HEX_LED
	mov		r0, #L7SEG_S & L7SEG_Dot
#endif
	mov		r1, #L7SEG_1 & L7SEG_Dot
	bl		SevenSegDisplay

	bl		SIZEDimm

/*** DRAM Initialization ***/
	ldr		r9, =I80312_BASE			/* 80312 Base address */

/* Set SDRAM Base Address */
        ldr             r0, =IQ80310_SDRAM_BASE_ADRS
        str             r0, [r9, #I80312_INDEX_SDBR]            /* Set SDRAM Base Address */

/* Set up bank 0 register */
CHECK_32MB:
        ldr             r1, =RAM_32MEG  /* do we have 32 MB banks? */
        cmp             r10, r1
        bne             CHECK_64MB
        ldr             r0, =SBR_32MEG  /* Program SDRAM Bank0 Boundary register to 32MB */
        b               SET_BANK1

CHECK_64MB:
        ldr             r1, =RAM_64MEG  /* do we have 64 MB banks? */
        cmp             r10, r1
        bne             CHECK_128MB
        ldr             r0, =SBR_64MEG  /* Program SDRAM Bank0 Boundary register to 64MB */
        b               SET_BANK1

CHECK_128MB:
        ldr             r1, =RAM_128MEG  /* do we have 128 MB banks? */
        cmp             r10, r1
        bne             CHECK_256MB
        ldr             r0, =SBR_128MEG /* Program SDRAM Bank0 Boundary register to 128MB */
        b               SET_BANK1

CHECK_256MB:
        ldr             r1, =RAM_256MEG  /* do we have 256 MB banks? */
        cmp             r10, r1
        bne             dram_error
        ldr             r0, =SBR_256MEG /* Program SDRAM Bank0 Boundary register to 256MB */
        b               SET_BANK1

dram_error:
#ifdef SECOND_HEX_LED
        mov             r0, #L7SEG_E
#endif
        mov             r1, #L7SEG_r
        bl              SevenSegDisplay
	b		dram_error

SET_BANK1:
        str             r0, [r9, #I80312_INDEX_SBR0]     /* store SBR0 */

        ldr             r2, =0x02
        cmp             r2, r6                          /* do we have 2 banks??? */
        bne             NO_BANK2

        add             r0, r0, r0                      /* SDRAM Bank1 Boundary register is double SBR0 */
        str             r0, [r9, #I80312_INDEX_SBR1]
        b               DISPLAY_DRAM

NO_BANK2:
        /* SDRAM Bank1 Boundary register is same as SBR0 for 1 bank configuration */
        str             r0, [r9, #I80312_INDEX_SBR1]     /* store SBR1 */

DISPLAY_DRAM:
        mov     r3, r0

SHOW_32MB:
        mov     r1, #SBR_32MEG
        cmp     r3, r1
        bne     SHOW_64MB
/* Display 32MB */
        bl      PrintString
        .ascii  "\nDRAM Size 32M \0"
        .align 2
#ifdef SECOND_HEX_LED
        mov     r0, #L7SEG_3
        mov     r1, #L7SEG_2
        bl      SevenSegDisplay
#endif
        b       END_DRAM_SIZE

SHOW_64MB:
        mov     r1, #SBR_64MEG
        cmp     r3, r1
        bne     SHOW_128MB
/* Display 64MB */
        bl      PrintString
        .ascii  "\nDRAM Size 64M \0"
        .align 2
#ifdef SECOND_HEX_LED
        mov     r0, #L7SEG_6
        mov     r1, #L7SEG_4
        bl      SevenSegDisplay
#endif
        b       END_DRAM_SIZE

SHOW_128MB:
        mov     r1, #SBR_128MEG
        cmp     r3, r1
        bne     SHOW_256MB
/* Display 128MB */
        bl      PrintString
        .ascii  "\nDRAM Size 128M \0"
        .align 2
#ifdef SECOND_HEX_LED
        mov     r0, #L7SEG_2
        mov     r1, #L7SEG_8
        bl      SevenSegDisplay
#endif
        b       END_DRAM_SIZE

SHOW_256MB:
        mov     r1, #SBR_256MEG
        cmp     r3, r1
        bne     SHOW_512MB
/* Display 256MB */
        bl      PrintString
        .ascii  "\nDRAM Size 256M \0"
        .align 2
#ifdef SECOND_HEX_LED
        mov     r0, #L7SEG_5
        mov     r1, #L7SEG_6
        bl      SevenSegDisplay
#endif
        b       END_DRAM_SIZE

SHOW_512MB:
/* Display 512MB */
        bl      PrintString
        .ascii  "\nDRAM Size 512M \0"
        .align 2
#ifdef SECOND_HEX_LED
        mov     r0, #L7SEG_1
        mov     r1, #L7SEG_2
        bl      SevenSegDisplay
#endif

END_DRAM_SIZE:

        bl      PrintString
        .ascii  "\n"
        .ascii  "=============================\n"
        .ascii  "= Memory Auto-Sized...      =\n"
        .ascii  "=============================\n\0"
        .align 2

        mov     r0, r3

init_dram:

/* Disable refresh Cycles */
	mov		r0, #I80312_SDRAM_REFRESH_DISABLE
	str		r0, [r9, #I80312_INDEX_RFR]		/* Disable Refresh Cycle */

/* Issue a NOP Command to all SDRAM devices */
	mov		r0, #I80312_SDRAM_CMD_NOP
	str		r0, [r9, #I80312_INDEX_SDIR]		/* Issue NOP cmd to SDRAM */
	DELAY(0x4000, r0)

/* Send a PrechargeAll Command to all SDRAM devices */
	mov		r0, #I80312_SDRAM_CMD_PCA
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Precharge all */
	DELAY(0x4000, r0)

	mov		r0, #I80312_SDRAM_CMD_AR
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #1 */
	DELAY(0x4000, r0)

/* Send 8 AutoRefresh Command. There should Trc cycles between every AutoRefresh */
	mov		r0, #I80312_SDRAM_CMD_AR
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #1 */
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #2 */
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #3 */
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #4 */
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #5 */
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #6 */
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #7 */
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Auto Refresh #8 */

/* Send Mode Reg Set Cmd with CAS Latency 2 */
	mov		r0, #I80312_SDRAM_CMD_MRS0
	str		r0, [r9, #I80312_INDEX_SDIR]	/* Send MRS Command */
	DELAY(0x4000, r0)

	ldr		r0, =0x00000006
	str		r0, [r9, #0x00000000]	        /* Issue aNormal Operation command */

/* Set Initial SDRAM Refesh rate */
	ldr		r0, =IQ80310_SDRAM_RFR_INIT_VAL
	str		r0, [r9, #I80312_INDEX_RFR]	/* Set Refresh Rate */

        bl      PrintString
        .ascii  "\n"
        .ascii  "=============================\n"
        .ascii  "= DRAM Initialized...       =\n"
        .ascii  "=============================\n\0"
        .align 2

/* End of BUS2 */
#ifdef SECOND_HEX_LED
	mov		r0, #L7SEG_S & L7SEG_Dot
#endif
	mov		r1, #L7SEG_2 & L7SEG_Dot
	bl		SevenSegDisplay

/* Enable Coprocessors CP0 and  CP13 access */
        ldr             r0, =0x2001
        mcr             p15, 0, r0, c15, c1, 0

        mcr             p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
        CPWAIT(r0)                              /* wait for the write to happen */

/* Invalidate I-Cache, D-Cache, and BTB */
        mcr             p15, 0, r0, c7, c7, 0
        CPWAIT(r0)                              /* Wait */

/* Enable Instruction Cache */
        mrc             p15, 0, r0, c1, c0, 0   /* Read Control Register*/
        orr             r0, r0, #0x1000         /* Set I-Cache bit */
        mcr             p15, 0, r0, c1, c0, 0   /* Write Back Control Register */
        CPWAIT(r0)                              /* Wait */

/*** MMU Setup ***/
/* Set Translation Table Base */
	ldr	        r0, =MMU_TRANSLATION_BASE
	mcr	        p15, 0, r0, c2, c0, 0	/* Set Translation Table Base Register */

/* Invalidate Instruction, Data TLBs */
        mcr     p15, 0, r0, c8, c7, 0   /* Flush I & D TLBs*/
        CPWAIT(r0)                      /* Wait */

/* Set Domain Access Control Register */
	ldr	        r0, =0xffffffff		/* Set All 16 domains to manager access */
	mcr	        p15, 0, r0, c3, c0, 0	/* Set Domain Permissions */

/* Enable MMU */
	mrc	        p15, 0, r0, c1, c0, 0	/* Read Control Register */
	orr	        r0, r0, #0x00000001     /* Enable MMU */
	mcr	        p15, 0, r0, c1, c0, 0	/* Write Back the Control Register */
	CPWAIT(r0)							/* Wait */

        bl      PrintString
        .ascii  "\n"
        .ascii  "=============================\n"
        .ascii  "= MMU Up and Initialized... =\n"
        .ascii  "=============================\n\0"
        .align 2