rominit.s

VXWORKS BSP开发包,初始化 驱动文件

/* romInit.s - vxWorks IQ80310 initialization module */

/* Copyright 1989-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01m,21jun02.scm modify warm boot for proper reboot 
01l,12nov01,j_b replaced assembly .MACROs w/ C preprocessor #define macros
01k,18oct01,jb  Enabling removal of pre-pended underscores for new compilers
                 (Diab/Gnu elf)
01j,27jul01,scm modify for extended page support...
01i,12apr01,scm debug pci...
01h,06apr01,scm fix table for 512M...
01g,24mar01,scm re-position of warm boot branch ...
01f,23mar01,scm move delay after PCI reset
01e,22mar01,scm change "r" to "S" for hex debug display
01d,22mar01,scm ECC initialization for rev d1 HW...
01c,21mar01,scm modify auto ram size to better support multi-bank SRAM...
01b,20mar01,scm PCI config bits...
01a,20mar01,scm add hex display to show autosized mem...
01e,26jan01,scm seperate IRQ & FIQ in vector table...
01d,18jan01,scm correct startup boot warm/cold...
01c,10jan01,scm modify startType...
01b,12dec00,scm correct cache settings
01a,20nov00,scm dimm auto resizing
*/

/*
DESCRIPTION

This module implements the low-level start up code for the iq80321 board.

When USE_RAM_HANDLERS not defined the following ERRORS can be deisplayed:

Fatal errors occurring during early initialization are signaled by
a two-digit code written to the board's LED display.

The following error codes are defined:

E0 - undefined instruction exception
E1 - software interrupt exception
E2 - prefetch abort exception
E3 - data abort exception
E4 - unrecognized exception (vector at 0x14)
E5 - IRQ exception
E6 - FIQ exception

*/

#define _ASMLANGUAGE

#include "vxWorks.h"
#include "arch/arm/arm.h"
#include "sysLib.h"
#include "config.h"

        .data
        .globl   VAR(copyright_wind_river)
        .long    VAR(copyright_wind_river)

/*** Local macros ***/
#undef USE_RAM_HANDLERS

/*** Local defines ***/
#ifdef SECOND_HEX_LED
/* use LSB 7-segment for debug display */
#define HEX_DISPLAY2               IQ80310_7SEG_BASE_MSB
#define HEX_DISPLAY1               IQ80310_7SEG_BASE_LSB
#else
/* use MSB 7-segment for debug display */
#define HEX_DISPLAY1               IQ80310_7SEG_BASE_LSB
#endif

#ifdef SECOND_UART
/* use UART #2 for debug display */
#define SERIAL_DISPLAY             IQ80310_UART_BASE_UART2
#else
/* use UART #1 for debug display */
#define SERIAL_DISPLAY             IQ80310_UART_BASE_UART1
#endif

/***** UART ****/

#define DMABodgeDelay              0x0A
#define UARTLCR_DivisorLatchAccess 0x80
#define UART_LineControl           0x03
#define BaudRateDivisor_115200     0x01
#define BaudRateDivisor_57600      0x02
#define UART_DivisorLatchLSB       0x00
#define UART_DivisorLatchMSB       0x01
#define UARTLCR_CharLength8        0x03
#define UARTLCR_StopBits1          0x00
#define UART_InterruptEnable       0x01
#define UARTFCR_Enable             0x01
#define UART_FIFOControl           0x02
#define UARTFCR_RXReset            0x02
#define ARTFCR_TXReset             0x04
#define UARTFCR_Mode0RXRDYTXRDY    0x00
#define UARTFCR_RXTrigger1         0x00
#define UARTMCR_DTRActive          0x01
#define UART_ModemControl          0x04
#define UART_LineStatus            0x05
#define UART_Transmit              0x00
#define UARTLSR_TXHoldingEmpty     0x20

#define IMMED1  #1
#define DELAY(cycles, reg0)          \
        ldr     reg0, =cycles ;      \
        subs    reg0, reg0, IMMED1 ; \
        subne   pc,  pc, IMMED12 ;

        .data
        .align 4

        .globl  VAR(sdata)      /* start of data */
        .globl  _sdata

_sdata:
VAR_LABEL(sdata)
        .asciz  "start of data seg"

        .text
        .align  4

        /* externals */
        .extern FUNC(romStart)  /* system initialisation routine */
        .extern _romStart

        /* globals */
        .globl  FUNC(romInit)
        .globl  _start
        .globl  _romInit
        .globl  _vectorTable
        .globl	FUNC(sysRomVecUndefInstuc)
        .globl	FUNC(sysRomVecSoftwareInt)
        .globl	FUNC(sysRomVecPrefetchAbort)
        .globl	FUNC(sysRomVecDataAbort)
        .globl	FUNC(sysRomVecUnknow)
        .globl	FUNC(sysRomVecIRQ)
        .globl	FUNC(sysRomVecFIQ)
        .globl  _sysRomVecDefault
        .globl  SevenSegDisplay

_start:

/*******************************************************************************
*
* vectorTable - vector jump tabel
*
*/

/* All vectors destroys r0, r1, and r2 */

	/* Register Usage:
	* r0 contains the vector number but used for temp use
	* r1 should contain the vector number in 7seg format
	* r2 Used for temp use
	*/

_vectorTable:
	ldr	pc, =ROM_TEXT_ADRS
	B	FUNC(sysRomVecUndefInstuc)
	B	FUNC(sysRomVecSoftwareInt)
	B	FUNC(sysRomVecPrefetchAbort)
	B	FUNC(sysRomVecDataAbort)
	B	FUNC(sysRomVecUnknow)
	B	FUNC(sysRomVecIRQ)
	B	FUNC(sysRomVecFIQ)

_ARM_FUNCTION(sysRomVecUndefInstuc)
#ifdef USE_RAM_HANDLERS
        ldr     pc, UNDEFINSInt
#else
        mov     r1, #L7SEG_0
        b       _sysRomVecDefault
#endif

_ARM_FUNCTION(sysRomVecSoftwareInt)
#ifdef USE_RAM_HANDLERS
        ldr     pc, SOFTWAREINTIsr
#else
        mov     r1, #L7SEG_1
        b       _sysRomVecDefault
#endif

_ARM_FUNCTION(sysRomVecPrefetchAbort)
#ifdef USE_RAM_HANDLERS
        ldr     pc, PREFETCHABORTIsr
#else
        mov     r1, #L7SEG_2
        b       _sysRomVecDefault
#endif

_ARM_FUNCTION(sysRomVecDataAbort)
#ifdef USE_RAM_HANDLERS
        ldr     pc, VECDATAABORTIsr
#else
        mov     r1, #L7SEG_3
        b       _sysRomVecDefault
#endif

_ARM_FUNCTION(sysRomVecUnknow)
#ifdef USE_RAM_HANDLERS
        ldr     pc, UNKNOWVECIsr
#else
        mov     r1, #L7SEG_4
        b       _sysRomVecDefault
#endif

_ARM_FUNCTION(sysRomVecIRQ)
#ifdef USE_RAM_HANDLERS
        ldr     pc, IRQRAMIsr
#else
        mov     r1, #L7SEG_5
        b       _sysRomVecDefault
#endif

_ARM_FUNCTION(sysRomVecFIQ)
#ifdef USE_RAM_HANDLERS
        ldr     pc, FIQRAMIsr
#else
        mov     r1, #L7SEG_6
        b       _sysRomVecDefault
#endif

	.balign 0x100, 0x0000

UNDEFINSInt:
	.long FUNC(sysRomVecUndefInstuc)

SOFTWAREINTIsr:
	.long FUNC(sysRomVecSoftwareInt)

PREFETCHABORTIsr:
	.long FUNC(sysRomVecPrefetchAbort)

VECDATAABORTIsr:
	.long FUNC(sysRomVecDataAbort)

UNKNOWVECIsr:
	.long FUNC(sysRomVecUnknow)

IRQRAMIsr:
	.long FUNC(sysRomVecIRQ)

FIQRAMIsr:
	.long FUNC(sysRomVecFIQ)


/*** Default Exception Handler ***/
/*
 * Doesn't do much, just displays 'E.' on the MSB 7-segment, and the
 * exception number on the LSB 7-segment display. Then goes into forever loop.
 */

/*
 * Register Usage:
 * r0 temp use
 * r1 contains the vector number in 7segment format
 * r2 Used for temp use
 */
_sysRomVecDefault:
#ifdef SECOND_HEX_LED
        mov     r0, #L7SEG_E & L7SEG_Dot
#endif
        bl      SevenSegDisplay
        b       _sysRomVecDefault

/*
 In I80310 (Coyanosa), for various reasons the MMU has to be enabled always.

- Caching Uint requires MMU
- The portion of the cache is used as internal data RAM, and since cache unit
  requires MMU, the MMU should be ON in order to access the internal data RAM.
*/

#ifdef _DIAB_TOOL

MakeTransTable: .macro addr,addrSize,options,total
    .if total
       .if total <= 0x40
           .long ((addr << addrSize) | options)
           MakeTransTable (addr+1), addrSize, options, (total-1)
       .else
           .if total <= 0x256
               MakeTransTable addr, addrSize, options, 0x40
               MakeTransTable (addr+0x40), addrSize, options, (total-0x40)
           .else
               MakeTransTable addr, addrSize, options, 0x256
               MakeTransTable (addr+0x256), addrSize, options, (total-0x256)
           .endif
       .endif
    .endif
    .endm

#else /* GNU */

.MACRO MakeTransTable addr=0,addrSize=0,options=0,total=0
.if \total
   .if \total <= 0x40
       .long ((\addr << \addrSize) | \options)
       MakeTransTable "(\addr+1)", \addrSize, \options, "(\total-1)"
   .else
       .if \total <= 0x256
           MakeTransTable \addr, \addrSize, \options, 0x40
           MakeTransTable "(\addr+0x40)", \addrSize, \options, "(\total-0x40)"
       .else
           MakeTransTable \addr, \addrSize, \options, 0x256
           MakeTransTable "(\addr+0x256)", \addrSize, \options, "(\total-0x256)"
       .endif
   .endif
.endif
.ENDM

#endif

/* Create First Level Section Descriptor */

#define SectionDesc(addr, options, total) \
        MakeTransTable addr, 20, options, total

/* Coarse page descriptor contains 14 bits, since it is easy to manipulate
 * the hex values, here the addr is shifted only by 12 bits, instead of 14bits.
 * So make sure that bit 11 and 10 are set to correctly in  options.
 * Bit 11 and 10 in options should contain the 2 LSBs from the coarse page address
 */

#define CoarsePageDesc(addr, options) \
        MakeTransTable addr, 12, options, 1

#define SmallPage(addr, options, total) \
        MakeTransTable addr, 12, options, total

	.balign MMU_TRANSLATION_BASE, 0x0000

#if defined(SECOND_LEVEL_PAGE_TABLE)
/* 1 + 2559 + 1512 + 24 = 4096 Entries */
/* First Level Coarse Page: address, options */
CoarsePageDesc(8, 0x00000001)            /* 1 : Coarse Entry */

/* First Level Section Descriptions: address, options, total */
SectionDesc(0x001, 0x00000c02, 0x9ff)    /* 2559 : ROM Entries */
#else
/* 2560 + 1512 + 24 = 4096 Entries */
SectionDesc(0x000, 0x00000c02, 0xa00)    /* 2560 : ROM Entries */
#endif
SectionDesc(0xa00, 0x00001e0e, 0x200)    /* RAM Entries */
SectionDesc(0xc00, 0x00001e02, 0x3e8)    /* RAM Entries */
SectionDesc(0xfe8, 0x00000c02, 0x18)     /* 24 : ROM Entries */

/* 0x8000 = 0x4000 + 4000 */

/* second level descriptors for fine page (4K) */
#if defined(SECOND_LEVEL_PAGE_TABLE)
/* Extended small page table definitions: address, options, total */
SmallPage(0xa0000, 0x0000007f, 0x1)  /* 1 : 4K Page for internal data RAM */
SmallPage(1, 0x00000073, 0x1)        /* 255 : 4K Page  for MMRs, and ROM */
SmallPage(2, 0x0000007f, 0xfe)       /* Remaning ROM */
#endif