📄 i80312pci.h
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UINT32 ATU_Configuration; /* 0x88 */ UINT32 ATU_reserved7; /* 0x8C */ UINT32 ATU_PrimaryInterrupt_Status; /* 0x90 */ UINT32 ATU_SecondaryInterrupt_Status; /* 0x94 */ UINT16 ATU_SecondaryCommand; /* 0x98 */ UINT16 ATU_SecondaryStatus; /* 0x9A */ UINT32 ATU_Secondary_Outbound_DAC_Window_Value; /* 0x9C */ UINT32 ATU_Secondary_Outbound_Upper_64_bit_DAC; /* 0xA0 *//* * NOTE: * The Configuration cycle registers are not included * in this structure to allow reading the structure * within the debugger. */ } ATU_CFG_SPACE;typedef struct { UINT32 ATU_primaryQueueControl; /* 0xb4 */ UINT32 ATU_secondaryQueueControl; /* 0xb8 */ UINT32 ATU_primaryInterruptMask; /* 0xbc */ UINT32 ATU_secondaryInterruptMask; /* 0xc0 */ } ATU_CFG_SPACE_END;typedef struct { UINT32 cfgType:2; UINT32 regNum:6; UINT32 funcNum:3; UINT32 devNum:5; UINT32 busNum:8; UINT32 regPos:2; UINT32 regLen:3; UINT32 reserved:2; UINT32 cfgEnable:1; } PCI_CFG;typedef struct { union { PCI_CFG bit; UINT32 whole; } u; } PCI_CFG_ADDR;#define CONFIG_WORD_PACK(type,reg,func,dev,bus,accessLen) \(type | (reg&0xfc)| ((func&0x7)<<8) | ((dev&0x1f)<<11) | ((bus&0xff)<<16) | \((reg&0x3)<<24) | ((accessLen&0x7)<<26) | 0x80000000)/* * type : configuration access type: TYPE 0 or TYPE 1 * reg: configuration space register address * func: device's function number * dev: device number * bus: PCI bus number where the device is sitting * accessLen: PCI_BYTE_ACCESS,PCI_UINT16_ACCESS and PCI_UINT32_ACCESS */#define CONFIG_REG_ADDR(cfgAddr,regAddr) \ cfgAddr.u.bit.regNum = regAddr >> 2; \ cfgAddr.u.bit.regPos = (regAddr&0x3)#define PCI_BYTE_ACCESS 1#define PCI_UINT16_ACCESS 2#define PCI_UINT32_ACCESS 4#define PCI_CFG_TYP0 0#define PCI_CFG_TYP1 1#define PRIMARY_BUS_INDEX 0#define SECONDARY_BUS_INDEX (PRIMARY_BUS_INDEX + 1)#define I80312_OUTBOUND_PRI_MEM_WIN 0x80000000#define I80312_OUTBOUND_SEC_MEM_WIN 0x88000000#define I80312_OUTBOUND_MEM_MASK 0x03FFFFFF#define I80312_OUTBOUND_PRI_IO_WIN 0x90000000#define I80312_OUTBOUND_SEC_IO_WIN 0x90010000#define I80312_OUTBOUND_IO_MASK 0x0000FFFF#define I80312_BRIDGE_CFG_BASE 0x1000#define I80312_ATU_CFG_BASE 0x1200/* Bridge control registers */#define BRIDGE_VIDR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x00)#define BRIDGE_DIDR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x02)#define BRIDGE_PCR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x04)#define BRIDGE_PSR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x06)#define BRIDGE_RID U8P_CAST (I80312_BRIDGE_CFG_BASE +0x08)#define BRIDGE_CCR U24P_CAST (I80312_BRIDGE_CFG_BASE +0x09)#define BRIDGE_PIF U8P_CAST (I80312_BRIDGE_CFG_BASE +0x09)#define BRIDGE_SUBCLASS U8P_CAST (I80312_BRIDGE_CFG_BASE +0x0A)#define BRIDGE_BASECLASS U8P_CAST (I80312_BRIDGE_CFG_BASE +0x0B)#define BRIDGE_CLSR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x0C)#define BRIDGE_PLTR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x0D)#define BRIDGE_HTR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x0E)#define BRIDGE_PBNR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x18)#define BRIDGE_SBNR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x19)#define BRIDGE_SubBNR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x1A)#define BRIDGE_SLTR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x1B)#define BRIDGE_IOBR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x1C)#define BRIDGE_IOLR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x1D)#define BRIDGE_SSR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x1E)#define BRIDGE_MBR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x20)#define BRIDGE_MLR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x22)#define BRIDGE_PMBR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x24)#define BRIDGE_PMLR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x26)#define BRIDGE_Cap_Ptr U8P_CAST (I80312_BRIDGE_CFG_BASE +0x34)#define BRIDGE_BCR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x3E)#define BRIDGE_EBCR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x40)#define BRIDGE_SISR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x42)#define BRIDGE_PBISR U32P_CAST (I80312_BRIDGE_CFG_BASE +0x44)#define BRIDGE_SBISR U32P_CAST (I80312_BRIDGE_CFG_BASE +0x48)#define BRIDGE_SACR U32P_CAST (I80312_BRIDGE_CFG_BASE +0x4C)#define BRIDGE_PIRSR U32P_CAST (I80312_BRIDGE_CFG_BASE +0x50)#define BRIDGE_SIOBR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x54)#define BRIDGE_SIOLR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x55)#define BRIDGE_SCDR U8P_CAST (I80312_BRIDGE_CFG_BASE +0x56)#define BRIDGE_SMBR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x58)#define BRIDGE_SMLR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x5A)#define BRIDGE_SDER U16P_CAST (I80312_BRIDGE_CFG_BASE +0x5C)#define BRIDGE_QCR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x5E)#define BRIDGE_Cap_ID U8P_CAST (I80312_BRIDGE_CFG_BASE +0x68)#define BRIDGE_Next_Item_Ptr U8P_CAST (I80312_BRIDGE_CFG_BASE +0x69)#define BRIDGE_PMCR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x6A)#define BRIDGE_PMCSR U16P_CAST (I80312_BRIDGE_CFG_BASE +0x6C)#define BRIDGE_PMCSR_BSE U8P_CAST (I80312_BRIDGE_CFG_BASE +0x6E)#define ATU_VID U16P_CAST (I80312_ATU_CFG_BASE + 0x00)#define ATU_DID U16P_CAST (I80312_ATU_CFG_BASE + 0x02)#define ATU_PATUCMD U16P_CAST (I80312_ATU_CFG_BASE + 0x04)#define ATU_PATUSR U16P_CAST (I80312_ATU_CFG_BASE + 0x06)#define ATU_RID U8P_CAST (I80312_ATU_CFG_BASE + 0x08)#define ATU_CCR U24P_CAST (I80312_ATU_CFG_BASE + 0x09)#define ATU_PIF U8P_CAST (I80312_ATU_CFG_BASE + 0x09)#define ATU_SUBCLASS U8P_CAST (I80312_ATU_CFG_BASE + 0x0A)#define ATU_BASECLASS U8P_CAST (I80312_ATU_CFG_BASE + 0x0B)#define ATU_CLSR U8P_CAST (I80312_ATU_CFG_BASE + 0x0C)#define ATU_LT U8P_CAST (I80312_ATU_CFG_BASE + 0x0D)#define ATU_HTR U8P_CAST (I80312_ATU_CFG_BASE + 0x0E)#define ATU_PIABAR U32P_CAST (I80312_ATU_CFG_BASE + 0x10)#define ATU_ASVIR U16P_CAST (I80312_ATU_CFG_BASE + 0x2C)#define ATU_ASIR U16P_CAST (I80312_ATU_CFG_BASE + 0x2E)#define ATU_ERBAR U32P_CAST (I80312_ATU_CFG_BASE + 0x30)#define ATU_Cap_Ptr U8P_CAST (I80312_ATU_CFG_BASE + 0x34)#define ATU_ILR U8P_CAST (I80312_ATU_CFG_BASE + 0x3C)#define ATU_IPR U8P_CAST (I80312_ATU_CFG_BASE + 0x3D)#define ATU_MGNT U8P_CAST (I80312_ATU_CFG_BASE + 0x3E)#define ATU_MLAT U8P_CAST (I80312_ATU_CFG_BASE + 0x3F)#define ATU_PIALR U32P_CAST (I80312_ATU_CFG_BASE + 0x40)#define ATU_PIATVR U32P_CAST (I80312_ATU_CFG_BASE + 0x44)#define ATU_SIABAR U32P_CAST (I80312_ATU_CFG_BASE + 0x48)#define ATU_SIALR U32P_CAST (I80312_ATU_CFG_BASE + 0x4C)#define ATU_SIATVR U32P_CAST (I80312_ATU_CFG_BASE + 0x50)#define ATU_POMWVR U32P_CAST (I80312_ATU_CFG_BASE + 0x54)#define ATU_POIOWVR U32P_CAST (I80312_ATU_CFG_BASE + 0x5C)#define ATU_PODWVR U32P_CAST (I80312_ATU_CFG_BASE + 0x60)#define ATU_POUDR U32P_CAST (I80312_ATU_CFG_BASE + 0x64)#define ATU_SOMWVR U32P_CAST (I80312_ATU_CFG_BASE + 0x68)#define ATU_SOIOWVR U32P_CAST (I80312_ATU_CFG_BASE + 0x6C)#define ATU_ERLR U32P_CAST (I80312_ATU_CFG_BASE + 0x74)#define ATU_ERTVR U32P_CAST (I80312_ATU_CFG_BASE + 0x78)#define ATU_Cap_ID U8P_CAST (I80312_ATU_CFG_BASE + 0x80)#define ATU_Next_Item_Ptr U8P_CAST (I80312_ATU_CFG_BASE + 0x81)#define ATU_APMCR U16P_CAST (I80312_ATU_CFG_BASE + 0x82)#define ATU_APMCSR U16P_CAST (I80312_ATU_CFG_BASE + 0x84)#define ATU_ATUCR U32P_CAST (I80312_ATU_CFG_BASE + 0x88)#define ATU_PATUISR U32P_CAST (I80312_ATU_CFG_BASE + 0x90)#define ATU_SATUISR U32P_CAST (I80312_ATU_CFG_BASE + 0x94)#define ATU_SATUCMD U16P_CAST (I80312_ATU_CFG_BASE + 0x98)#define ATU_SATUSR U16P_CAST (I80312_ATU_CFG_BASE + 0x9A)#define ATU_SODWVR U32P_CAST (I80312_ATU_CFG_BASE + 0x9C)#define ATU_SOUDR U32P_CAST (I80312_ATU_CFG_BASE + 0xA0)#define ATU_POCCAR U32P_CAST (I80312_ATU_CFG_BASE + 0xA4)#define ATU_SOCCAR U32P_CAST (I80312_ATU_CFG_BASE + 0xA8)#define ATU_POCCDR U32P_CAST (I80312_ATU_CFG_BASE + 0xAC)#define ATU_SOCCDR U32P_CAST (I80312_ATU_CFG_BASE + 0xB0)#define ATU_PAQCR U32P_CAST (I80312_ATU_CFG_BASE + 0xB4)#define ATU_SAQCR U32P_CAST (I80312_ATU_CFG_BASE + 0xB8)#define ATU_PATUIMR U32P_CAST (I80312_ATU_CFG_BASE + 0xBC)#define ATU_SATUIMR U32P_CAST (I80312_ATU_CFG_BASE + 0xC0)/* Primary ATU command register */#define PATUCMD_MEM_ENABLE 0x2/* private slot info */#define I80312_NUM_PRIVATE_SLOTS 15#define I80312_NUM_DEFAULT_PRIVATE 5#define I80312_DEFAULT_PRIVATE_MASK 0x1F#define I80312_PRIVATE_SLOT_MASK 0x3FF#define I80312_NUM_PRIVATE_SELECT 10/* ATU configuration register (0x1288) settings */#define ATUCR_PRI_OUTBOUND_ENABLE 0x0002#define ATUCR_SEC_OUTBOUND_ENABLE 0x0004#define ATUCR_BIST_ENABLE 0x0008#define ATUCR_PRI_PCI_ERROR_INT_ENABLE 0x0010#define ATUCR_SEC_PCI_ERROR_INT_ENABLE 0x0020#define ATUCR_EXPANSION_ROM_WIDTH 0x0040#define ATUCR_SEC_DIRECT_ADDR_SELECT 0x0080#define ATUCR_DIRECT_ADDR_ENABLE 0x0100#define ATUCR_SEC_OUTBOUND_FORWARD_ENABLE 0x0200#define ATUCR_SEC_PCI_BOOT_MODE 0x0800 #define ATUCR_BRIDGE_FUNC_NUM (1<<21)/* ATU IMR registers */#define PATUIMR_MASK 0xFC#define SATUIMR_MASK 0xFC#define ATUIMR_TARGET_ABORT_ENABLE 1/* Bridge Control Register settings */#define PARITY_ENABLE 0x0001#define SERR_ENABLE 0x0002#define ISA_ENABLE 0x0004#define VGA_ENABLE 0x0008#define MASTER_ABORT_MODE 0x0020#define SECONDARY_RESET 0x0040#define FAST_BACK_TO_BACK 0x0080/* Extended Bridge Control Register settings */#define POSTING_DISABLE 0x0001#define CORE_RESET 0x0002#define CFG_RETRY 0x0004#define UPSTREAM_PREFETCH_ENABLE 0x0008#define SYNC_MODE 0x0010#define LOCAL_RESET 0x0020#define SECONDARY_DAC_ENABLE 0x0040/* Secondary Bridge Interrupt Status Register */#define I80312_BRIDGE_TARGET_ABORT 0x02#define I80312_BRIDGE_MASTER_TARGET_ABORT 0x04#define I80312_BRIDGE_MASTER_ABORT 0x08/* Secondary Decode Enable Register (0x105C) settings */#define SDER_SECONDARY_BUS_RESET_INT_MASK 0x0008#define SDER_PRIMARY_DET_PARITY_INT_MASK 0x0010#define SDER_SECONDARY_DET_PARITY_INT_MASK 0x0020/* valid Secondary ATU Command Register settings */#define SCMD_MEM_ENABLE 0x00000002#define SCMD_BUS_MASTER_ENABLE 0x00000004#define SCMD_MWI_ENABLE 0x00000010#define SCMD_PARITY_CHECK_ENABLE 0x00000040#define SCMD_SERR_ENABLE 0x00000100#define SCMD_FAST_B_TO_B_ENABLE 0x00000200/* Zero maintains processor default arbitration. */#define I80312_SECONDARY_ARBITRATION_MASK 0x0#define I80312_PRIVATE_EXPANSION_DEFAULT 0x100000#define I80312_NUM_PRIVATE_SELECT 10/******************** I80312 specific PCI defines **********************/#define I80312_PRIVATE_INT_SIZE 10 /* interrupt pin routing table size *//* identify which PCI interface on the RP: Primary or Secondary */#define I80312_PCI_PRIMARY_MASTER 0#define I80312_PCI_SECONDARY_MASTER 1#define PCI_INTA 0#define PCI_INTB 1#define PCI_INTC 2#define PCI_INTD 3#define I80312_PRIVATE_DEVICE_SELECT 0x0F#define I80312_PCI_DEVICE_MAX_NUM 20#define NO_DEVICE 0#define FUNC0_DEVICE 1#define MULTI_FUNC_DEVICE 8/* address translation defines */#define I80312_INBOUND 0#define I80312_OUTBOUND 1#define I80312_MEM_WINDOW 0#define I80312_DAC_WINDOW 1#define I80312_DIRECT_WINDOW 2#define I80312_IO_WINDOW 3/* Outbound window defines */#define I80312_POUTB_SIZE 0x04000000#define I80312_POUTB_BASE 0x80000000#define I80312_SOUTB_SIZE 0x04000000#define I80312_SOUTB_BASE 0x88000000#define I80312_DOUTB_BASE 0x2000#define I80312_DOUTB_TOP 0x7fffffff#define I80312_POUTB_IO_BASE 0x90000000#define I80312_POUTB_IO_SIZE 0x10000#define I80312_SOUTB_IO_BASE 0x90010000#define I80312_SOUTB_IO_SIZE 0x10000#define I80312_POUTB_DAC_SIZE 0x04000000#define I80312_POUTB_DAC_BASE 0x84000000#define I80312_SOUTB_DAC_SIZE 0x04000000#define I80312_SOUTB_DAC_BASE 0x8C000000#ifndef _ASMLANGUAGE/* Node for list of base address register's and requirements */typedef struct { DL_NODE node; UINT32 memReq; PCI_CFG_ADDR cfgAddr; } PCI_BAR_NODE;typedef struct { /* dynamic address translation */ volatile UINT32 * tran; UINT32 range; UINT32 base; UINT32 current; /* one on one direct address translation */ int dTran; /* direct address translation, TRUE or FALSE */ UINT32 dBase; /* direct address translation base */ UINT32 dTop; /* direct address translation top address */ UINT32 dCurrent; /* PCI I/O space address translation */ volatile UINT32 * ioTran; UINT32 ioRange; UINT32 ioBase; UINT32 ioCurrent; /* PCI DAC memory space address translation */ volatile UINT32 * dacTran; UINT32 dacRange; UINT32 dacBase; UINT32 dacCurrent; } OUTBOUND_ADDRESS_TRAN;typedef struct { volatile UINT32 * tran; volatile UINT32 * limit; volatile UINT32 * base; } INBOUND_ADDRESS_TRAN;typedef struct { volatile UINT32 * addrReg; /* configuration cycle address register */ UINT32 dataReg; /* configuration cycle data register */ } I80312_PCI_CFG_REGS;typedef struct { UINT32 top; /* top address of the window */ UINT32 base; /* base address of the window */ } I80312_WINDOW_TOP_BASE;extern UINT32 i80312_PriBusNumber;extern UINT32 i80312_SecBusNumber;extern UINT32 i80312_SubBusNumber;extern UINT32 i80312_BusNumbers[];#if defined(__STDC__) || defined(__cplusplus)extern void i80312PrivateDevInit(void);extern void pciConfigQuery(int , PCI_CFG_ADDR , UINT32 *);extern void sysPciInit (void);extern int i80312PciDeviceProbe (int busMaster, PCI_CFG_ADDR cfgAddr);extern void i80312PciSecIntSet (UINT8 slot,UINT8 xintA,UINT8 xintB,UINT8 xintC, UINT8 xintD);extern STATUS i80312PciFindDevice (int vendorId, int deviceId, int index, UINT32 * pBusNo, UINT32 * pDeviceNo, UINT32 * pFuncNo);extern int i80312PciCfgRd (int,PCI_CFG_ADDR,UINT32 * );extern int i80312PciCfgWr (int,PCI_CFG_ADDR, UINT32);extern STATUS pciDeviceFind (int,int, int, int *, int *, int *);extern STATUS pciConfigInByte (int, int, int, int, char * );extern STATUS pciConfigInWord (int, int, int, int, short * );extern STATUS pciConfigInLong (int, int, int, int, int *);extern STATUS pciConfigOutByte (int, int, int, int, char);extern STATUS pciConfigOutWord (int, int, int, int, short);extern STATUS pciConfigOutLong (int, int, int, int, int);#else /* __STDC__ */extern void i80312PciAutoConfig();extern void pciConfigQuery();extern void sysPciInit ();extern void sysPciInit2 ();extern int i80312PciDeviceProbe ();extern void i80312PciSecIntSet ();extern STATUS i80312PciFindDevice ();extern int i80312PciCfgRd ();extern int i80312PciCfgWr ();extern STATUS pciDeviceFind ();extern STATUS pciConfigInByte ();extern STATUS pciConfigInWord ();extern STATUS pciConfigInLong ();extern STATUS pciConfigOutByte ();extern STATUS pciConfigOutWord ();extern STATUS pciConfigOutLong ();#endif /* __STDC__ */#endif /* _ASMLANGUAGE */#ifdef __cplusplus}#endif#endif /* __INCi80312Pcih */⌨️ 快捷键说明
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