target.nr

VXWORKS BSP开发包,初始化 驱动文件

Please consult the Intel XScale Core Developer's Manual for more
information on the extended page table and X bit support.

.SS "Building a visionProbe Debuggable Image"

One can build an image to work with visionClick/Probe as a standalone image 
by including "INCLUDE_HSI_PROBE" in config.h.  

If "INCLUDE_HSI_PROBE" defined, then define "STANDALONE_NET", and undefine 
"INCLUDE_FLASH"...  also flush out DEFAULT_BOOT_LINE for IPs and target name,
all of which is done in config.h.

Once these are defined, perform a "make vxWorks.st".

For visionClick/Probe you must convert your vxWorks.st into a "bdx" image...

Example:
 convert.exe "Z:\wpwr\target\config\iq80310\vxWorks.st" -c -m gnu -b -z

 under visionClick/Probe GUI, select from menu bar: " TOOLS/CONVERT OBJECT MODULES",
 and :
   (1) add path to vxWorks.st image,
   (2) check "create symbol file for visionClick"
   (3) check "create bdx file for RAM download"

.SS "Timestamp support"
At the time of development, the iq80310 development board has no
functioning spare timers and therefore requires timestamps to be derived
from the VxWorks system clock timer.

There is no support for the auxiliary clock. bspVal testing will be skipped
when auxiliary clock required. Also note, the timestamp timer is timed to
the system clock. This implies that you will not be able to enable/disable
the timestamp timer, it is free running while the system clock is enabled.
bspVal tests which enable/disable the timestamp timer will fail (and are
expected too).

.SS "Rotary Switch"
The BSP uses the rotary switch to determine whether the iq80310
is plugged into a PC or a standalone backplane.  PCI configuration is 
slightly different depending on the configuration.  When plugged into
a PC, the PCI interface numbers are assigned by the PC's ROM bios.  When 
plugged into a standalone backplane, the board is considered the "master" 
and assigns its own interface numbers.  When the switch is set to position 
#7, the BSP assumes the board is in a PC backplane.  When set to position 
#6, the board is assumed to be in a standalone backplane.

.SS "CPU Speed/Timers"
The iq80310 BSP/development board does not support an auxillary clock.  
The current system has no suitable spare timers and requires timestamps to 
be derived from the VxWorks system clock timer.

.bS
                        _______
hardware                TIMER 0
clock                   _______
                           |
interface -----------------------------------------------------
                |                 |                  |
                |                 |                  |
software     _______            ______          _____________
clock(s)     sysClk             auxClk          timeStampClk
             _______            ______          _____________
.bE

.SS "Special routines"
There is a two digit hex-display, with each digit composed of seven 
segments, on the iq80310 development board which may aid in user debug.  
Control methods are provided in the BSP-specific header file, iq80310.h.

.bS
 7 Segment LCDs  MSB/LSB 
 0-On, 1-Off

          A1/2
          Bit 0
        ---------
       |        |
 F1/2  |        | B1/2
 Bit 5 |        | Bit 1
       | G1/2   |
       | Bit 6  |
        ---------
       |        |
 E1/2  |        | C1/2
 Bit 4 |        | Bit 2
       | D1/2   |
       | Bit 3  |       DP1/2
        ---------     * Bit 7 (dot)
.bE

.SS "Divide by Zero Exception"
The ARM architecture does not provide for an integer divide by zero
exception.  Consequently, no exception is generated when an integer
divide by zero operation is performed programmatically.

.SS "iq80310 DEVELOPMENT BOARD DETAILS"
.SS "Board Layout"
The diagrams below show the relevant jumpers for VxWorks
configuration.
.bS

________________________________________________                                
|         +---------------------------+        |                               
|         | Secondary PCI Slot - (J5) |        |                             
|         |            Right Angle    |        |                          
|         +---------------------------+        |                         
|         +---------------------------+        |                       
|         | Secondary PCI Slot (J1)   |        |                      
|         +---------------------------+        |                    
|                                              |                   
|              +--------+        +---------+   |                  
|              |        |        |         |   |
|              | 21154  |        |   HEX   |   |
|              |  PCI   |        | Display |   |
|              | Bridge |        |  (CR1)  |   |
|              |  (U1)  |        |         |   |
|              |        |        +---------+   |                     COM1   COM2
|              +--------+                      |                    SERIAL SERIAL
|   +---------------------------------+        __________++++++++___++++++_++++++_
|   | 168-Pin SDRAM DIMM Socket (J6)  | +---+            | LEDs |   | J9 | |J10 ||                      
|   +---------------------------------+ |SW |            |______|   |____| |____||                    
|                                       | #1|                                    |                   
|   +---------------------------------+ +---+                                    |                       
|   | Logic Analyzer Motor Connector  |  +------------+                          |                      
|   |   (J11 thru J15)                |  | JTAG       |                          |                    
|   +---------------------------------+  | Connectors |                          |
|                                        +------------+ +--------+               |
|                    +------------+                     |        |               |
|                    |            |                     |  CPLD  |               |
+----------+         |  INTEL     |                     |  (U17) |               |
+ Ethernet |         |            |  +--------+         +--------+               |
+  Port    |         |  iq80312   |  | INTEL  |                    +----------+  |
+  (J18)   |         |            |  | iq80200|      +---+         |          |  |
+----------+   +---+ |  (U18)     |  |  (U19) |      |SW |         |          |  |
|              |SW | +------------+  +--------+      | #3|         |  Li-ion  |  |
|              | #2|         +---+                   +---+         |  Battery |  |
|              +---+         |SW |                                 |   (U30)  |  |
|                            | #4|                                 |          |  |
|                            +---+                                 +----------+  |
|  +______+    +_+            +_+  +_+      +____________________________________| 
|__|      |____| |____________| |__| |______|                                   

             64-Bit PCI

.bE
Key:

    SW1     Rotary switch
    SW2     PCI Bus Speed switch
    SW3     Programming Mode switch
    SW4     Not currently in use

    J6      168-Pin SDRAM DIMM Socket
    J9/10   Serial Ports
    J1      Secondary PCI Slot             
    J5      Secondary PCI Slot -Right Angle 
    J18     Ethernet Port          
    J11-15  Logic Analyzer Motor Connector
    U1      21154 PCI Bridge
    U17     CPLD
    U19     Intel iq80200
    U18     Intel iq80312
    U30     Li-ion Battery
    CR1     HEX Display

.SS "Jumpers"
The following jumpers and switches are relevant to VxWorks configuration.

'Switch S1 Settings:'

.TS
expand;
1 1 .
Position | Description
_
0 | Flash Monitor
1 | Redboot
2 | Angel
3 | Angel
4 | Wind River IxWorks
5 | Wind River IxWorks
6 | VxWorks when installed in a passive backplane
7 | VxWorks when installed in a PC backplane
.TE


'Switch S2 Settings:'

.TS
expand;
1 1 1 1 .
Position | Name | Description | Default
_
S2-1 | P_M66EN | User may force the primary PCI but 
               | to start at 33 MHz mode.  
               | ON = forces P-PCI to run at 33 MHz.  | OFF
S2-2 | S_M66EN | User may force the secondary PCI but 
               | to start at 33 MHz mode.  
               | ON = forces S-PCI to run at 33 MHz.  | OFF
S2-3 | -- | NC | OFF
S2-4 | -- | NC | OFF
.TE

Note: If S2-1 is ON, then S-PCI will run at 33 MHz.


'Switch S3 Settings:'

.TS
expand;
1 1 1 1 .
Position | Name | Description | Default
_
S3-1 | RST_MODE#    | Determines if the core is to be held in RESET.  
                    | ON  = hold in RESET.  
					| OFF = allows processor initialization.  
					| When programming the flash using a utility that uses the 
					| primary PCI, turn the switch ON for programming mode.  | OFF
S3-2 | RETRY        | Determines if the Primary PCI Interface will be disabled.  
                    | ON  = allows Primary PCI configuration cycles to occur.  
					| OFF = retries all Primary PCI configuration cycles.  
					| When programming the flash using a utility that uses the 
					| primary PCI, turn the switch ON for programming mode.  | OFF
S3-3 | SPMEM#       | Special Downstream Window enable.  If enabled, a special 
                    | downstream memory window FEC0 0000h through FECF FFFFh 
					| is opened.  
					| ON  = enabled.  
					| OFF = disabled.  | OFF
S3-4 | 32BITPCI_EN# | Determines whether Secondary PCI bus is a 32- or 64-bit bus.  
                    | ON  = indicates Secondary PCI bus is a 32-bit bus.  
					| OFF = indicates Secondary PCI bus is a 64-bit bus.  | OFF
.TE

'Switch S4 Settings:'


.TS
expand;
1 1 1 1 .
Position | Name | Description | Default
_
S4-1 | CINT_SW | (REV F or later) When ON, the FIQ/IRQ routing between the 80200 and 80312 is straight through.  
               | When OFF, the lines are reversed. Prior to Rev F boards, this switch was not used.  | OFF
S4-2 |   --    | Not Used | ---
S4-3 |   --    | Not Used | ---
S4-4 |   --    | Not Used | ---
.TE

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration."

.SH "BIBLIOGRAPHY"
.I "Intel XScale Core Developers Manual",
.I "Intel 80200 Processor based Intel XScale Microarchitecture Developer's Manual",
.I "Intel 80200 Processor based Intel XScale Microarchitecture Datasheet",
.I "Intel 80200 Processor based Intel XScale Microarchitecture Specifications Update",
.I "Intel 80310 I/O Processor Chipset with Intel XScale  Microarchitecture Design Guide",
.I "Intel 80312 I/O Companion Chip Developer's Manual",
.I "Intel 80312 I/O Companion Chip Datasheet",
.I "Intel 80312 I/O Companion Chip Specificarion Update",
.I "Intel 82559 Fast Ethernet Multifunction PCI/Card Bus Controller",
.I "Intel 80310 I/O Processor Chipset with Intel XScale Mich`roarchitecture Initialization",
.I "Intel XScale Microarchitecture, Programmers Reference Manual",
.I "PCI Local Bus Specification, Revision 2.2 (www.pcisig.com)",
.I "GNUPro Toolkit Documentation",
.I "UART PN#TL16C550C Documentation: Texas Instrument",
.I "Intel I/O Processors Comprehensive Documentation: IQ80310 Development CD".