i80312intrctl.h

VXWORKS BSP开发包,初始化 驱动文件

/* i80312IntrCtl.h - interrupt controller driver for Yavapai(80312) */

/* Copyright 2000 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,14may01,scm  fix secondary PCI interrupt...
01b,13apr01,scm  debug pci...
01a,05sep00,scm  written.
*/

#ifndef	__INCi80312IntrCtlh
#define	__INCi80312IntrCtlh

#ifdef __cplusplus
extern "C" {
#endif

/*
  Yavapai has four external interrupts XINT0, XINT1, XINT2, and XINT3. And
   They have two XINT6, and XINT7 internal source of multiplexed
   interrupts. We are going assume like this

   o There are totally 8 level of interrupts XIN0-XINT7 and each interrupt can
      be multiplexed upto to 32 levels.

   o XINT4, abd XINT5 are reserved

*/

/*** Need to be inside the BSP ***/

#define I80312INT_IND_XINT0	0
#define I80312INT_IND_XINT1	1
#define I80312INT_IND_XINT2	2
#define I80312INT_IND_XINT3	3
#define I80312INT_IND_XINT4	4
#define I80312INT_IND_XINT5	5
#define I80312INT_IND_XINT6	6
#define I80312INT_IND_XINT7	7
#define I80312INT_IND_MAX	8

#define I80312INT_LVL_MULTPLEX	32
#define I80312INT_MAX_LEVELS	(I80312INT_IND_MAX*I80312INT_LVL_MULTPLEX)  /* 256 */
#define I80312INT_MODE		INT_NON_PREEMPT_MODEL
#define I80312INT_INUM_TO_IVEC(level)	(level)

#define I80312INT_LVL_BASE_XINT0 (I80312INT_IND_XINT0*I80312INT_LVL_MULTPLEX)  /*   0 */
#define I80312INT_LVL_BASE_XINT1 (I80312INT_IND_XINT1*I80312INT_LVL_MULTPLEX)  /*  32 */
#define I80312INT_LVL_BASE_XINT2 (I80312INT_IND_XINT2*I80312INT_LVL_MULTPLEX)  /*  64 */
#define I80312INT_LVL_BASE_XINT3 (I80312INT_IND_XINT3*I80312INT_LVL_MULTPLEX)  /*  96 */
#define I80312INT_LVL_BASE_XINT4 (I80312INT_IND_XINT4*I80312INT_LVL_MULTPLEX)  /* 128 */
#define I80312INT_LVL_BASE_XINT5 (I80312INT_IND_XINT5*I80312INT_LVL_MULTPLEX)  /* 160 */
#define I80312INT_LVL_BASE_XINT6 (I80312INT_IND_XINT6*I80312INT_LVL_MULTPLEX)  /* 192 */
#define I80312INT_LVL_BASE_XINT7 (I80312INT_IND_XINT7*I80312INT_LVL_MULTPLEX)  /* 224 */

#define I80312INT_LVL_MAX_XINT2  (I80312INT_LVL_BASE_XINT2+I80312INT_LVL_MULTPLEX-1)  /*  95 */
#define I80312INT_LVL_MAX_XINT3  (I80312INT_LVL_BASE_XINT3+I80312INT_LVL_MULTPLEX-1)  /* 127 */
#define I80312INT_LVL_MAX_XINT7  (I80312INT_LVL_BASE_XINT7+I80312INT_LVL_MULTPLEX-1)  /* 255 */

/* Not required if defined in some other file.*/
#define I80312INT_BIT_0		0
#define I80312INT_BIT_1		1
#define I80312INT_BIT_2		2
#define I80312INT_BIT_3		3
#define I80312INT_BIT_4		4
#define I80312INT_BIT_5		5
#define I80312INT_BIT_6		6
#define I80312INT_BIT_7		7

#define I80312INT_LVL_ALL_DISABLED	0
#define I80312INT_LVL_ALL_ENABLED	(I80312INT_MAX_LEVELS-1)  /* 255 */

/*** Interrupt levels ***/
/* XINT0-3 Interrupts */

#define I80312INT_VEC_SPCIA	(I80312INT_LVL_BASE_XINT0+I80312INT_BIT_0)  /*   0 */   
#define I80312INT_VEC_SPCIB	(I80312INT_LVL_BASE_XINT1+I80312INT_BIT_0)  /*  32 */
#define I80312INT_VEC_SPCIC	(I80312INT_LVL_BASE_XINT2+I80312INT_BIT_0)  /*  64 */
#define I80312INT_VEC_SPCID	(I80312INT_LVL_BASE_XINT3+I80312INT_BIT_4)  /* 100 */

/* XINT3 Interrupts */

#define I80312INT_VEC_TIMER	(I80312INT_LVL_BASE_XINT3+I80312INT_BIT_0)  /*  96 */
#define I80312INT_VEC_ETHERNET	(I80312INT_LVL_BASE_XINT3+I80312INT_BIT_1)  /*  97 */
#define I80312INT_VEC_UART1	(I80312INT_LVL_BASE_XINT3+I80312INT_BIT_2)  /*  98 */
#define I80312INT_VEC_UART2	(I80312INT_LVL_BASE_XINT3+I80312INT_BIT_3)  /*  99 */
#define I80312INT_VEC_SPCII	(I80312INT_LVL_BASE_XINT3+I80312INT_BIT_4)  /* 100 */

/*** XINT6 Interrupts ***/

#define I80312INT_VEC_EOC_DMA0	(I80312INT_LVL_BASE_XINT6+I80312INT_BIT_0)  /* 192 */
#define I80312INT_VEC_EOC_DMA1	(I80312INT_LVL_BASE_XINT6+I80312INT_BIT_1)  /* 193 */
#define I80312INT_VEC_EOC_DMA2	(I80312INT_LVL_BASE_XINT6+I80312INT_BIT_2)  /* 194 */
#define I80312INT_VEC_PMU	(I80312INT_LVL_BASE_XINT6+I80312INT_BIT_4)  /* 196 */
#define I80312INT_VEC_AAU	(I80312INT_LVL_BASE_XINT6+I80312INT_BIT_5)  /* 197 */

/*** XINT7 Interrupts ***/

#define I80312INT_VEC_I2C	(I80312INT_LVL_BASE_XINT7+I80312INT_BIT_1)  /* 225 */
#define I80312INT_VEC_MU	(I80312INT_LVL_BASE_XINT7+I80312INT_BIT_2)  /* 226 */
#define I80312INT_VEC_BIST	(I80312INT_LVL_BASE_XINT7+I80312INT_BIT_3)  /* 227 */

/*** defs so that we can use the rpIntLib.c ***/

#define VECTOR_XINT0		I80312INT_VEC_SPCIA  /*   0 */
#define VECTOR_XINT1		I80312INT_VEC_SPCIB  /*  32 */
#define VECTOR_XINT2		I80312INT_VEC_SPCIC  /*  64 */
#define VECTOR_XINT3		I80312INT_VEC_SPCID  /* 100 */

/* Just to complie XINT4-7 are invalid */

#define XINT7                   7
#define XINT6                   6
#define XINT5                   5
#define XINT4                   4
#define XINT3                   I80312INT_VEC_SPCID  /* 100 */
#define XINT2                   I80312INT_VEC_SPCIC  /*  64 */
#define XINT1                   I80312INT_VEC_SPCIB  /*  32 */
#define XINT0                   I80312INT_VEC_SPCIA  /*   0 */

#define RP_VIRT_DMA0_VECTOR	I80312INT_VEC_EOC_DMA0  /* 192 */
#define RP_VIRT_DMA1_VECTOR	I80312INT_VEC_EOC_DMA1  /* 193 */
#define RP_VIRT_DMA2_VECTOR	I80312INT_VEC_EOC_DMA2  /* 194 */
#define RP_VIRT_AAU_VECTOR 	I80312INT_VEC_AAU       /* 197 */

/* Interrupt bits in INTSRC register */
#define I80200_INTSRC_MASK        0xF0000000

/* typedefs */

#ifndef _ASMLANGUAGE
#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif	/* __INCi80312IntrCtl */