san_led.map.qmsg

动态流水灯显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 14 11:08:20 2009 " "Info: Processing started: Tue Apr 14 11:08:20 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off san_led -c san_led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off san_led -c san_led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "san_led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file san_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 scan_led " "Info: Found entity 1: scan_led" {  } { { "san_led.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/san_led.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "scan_led scan_led.v(1) " "Error (10228): Verilog HDL error at scan_led.v(1): module \"scan_led\" cannot be declared more than once" {  } { { "scan_led.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/scan_led.v" 1 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "scan_led san_led.v(1) " "Info (10151): Verilog HDL Declaration information at san_led.v(1): \"scan_led\" is declared here" {  } { { "san_led.v" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/san_led.v" 1 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan_led.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file scan_led.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Error: Peak virtual memory: 153 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Tue Apr 14 11:08:32 2009 " "Error: Processing ended: Tue Apr 14 11:08:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:12 " "Error: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}