📄 main.dbg
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PORTB_BIT2: equ 2 ; Port B Bit 2
PORTB_BIT3: equ 3 ; Port B Bit 3
PORTB_BIT4: equ 4 ; Port B Bit 4
PORTB_BIT5: equ 5 ; Port B Bit 5
PORTB_BIT6: equ 6 ; Port B Bit 6
PORTB_BIT7: equ 7 ; Port B Bit 7
; bit position masks
mPORTB_BIT0: equ %00000001
mPORTB_BIT1: equ %00000010
mPORTB_BIT2: equ %00000100
mPORTB_BIT3: equ %00001000
mPORTB_BIT4: equ %00010000
mPORTB_BIT5: equ %00100000
mPORTB_BIT6: equ %01000000
mPORTB_BIT7: equ %10000000
;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
DDRAB: equ $00000002 ;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRAB_BIT0: equ 0 ; Data Direction Port AB Bit 0
DDRAB_BIT1: equ 1 ; Data Direction Port AB Bit 1
DDRAB_BIT2: equ 2 ; Data Direction Port AB Bit 2
DDRAB_BIT3: equ 3 ; Data Direction Port AB Bit 3
DDRAB_BIT4: equ 4 ; Data Direction Port AB Bit 4
DDRAB_BIT5: equ 5 ; Data Direction Port AB Bit 5
DDRAB_BIT6: equ 6 ; Data Direction Port AB Bit 6
DDRAB_BIT7: equ 7 ; Data Direction Port AB Bit 7
DDRAB_BIT8: equ 8 ; Data Direction Port AB Bit 8
DDRAB_BIT9: equ 9 ; Data Direction Port AB Bit 9
DDRAB_BIT10: equ 10 ; Data Direction Port AB Bit 10
DDRAB_BIT11: equ 11 ; Data Direction Port AB Bit 11
DDRAB_BIT12: equ 12 ; Data Direction Port AB Bit 12
DDRAB_BIT13: equ 13 ; Data Direction Port AB Bit 13
DDRAB_BIT14: equ 14 ; Data Direction Port AB Bit 14
DDRAB_BIT15: equ 15 ; Data Direction Port AB Bit 15
; bit position masks
mDDRAB_BIT0: equ %00000001
mDDRAB_BIT1: equ %00000010
mDDRAB_BIT2: equ %00000100
mDDRAB_BIT3: equ %00001000
mDDRAB_BIT4: equ %00010000
mDDRAB_BIT5: equ %00100000
mDDRAB_BIT6: equ %01000000
mDDRAB_BIT7: equ %10000000
mDDRAB_BIT8: equ %100000000
mDDRAB_BIT9: equ %1000000000
mDDRAB_BIT10: equ %10000000000
mDDRAB_BIT11: equ %100000000000
mDDRAB_BIT12: equ %1000000000000
mDDRAB_BIT13: equ %10000000000000
mDDRAB_BIT14: equ %100000000000000
mDDRAB_BIT15: equ %1000000000000000
;*** DDRA - Port A Data Direction Register; 0x00000002 ***
DDRA: equ $00000002 ;*** DDRA - Port A Data Direction Register; 0x00000002 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRA_BIT0: equ 0 ; Data Direction Port A Bit 0
DDRA_BIT1: equ 1 ; Data Direction Port A Bit 1
DDRA_BIT2: equ 2 ; Data Direction Port A Bit 2
DDRA_BIT3: equ 3 ; Data Direction Port A Bit 3
DDRA_BIT4: equ 4 ; Data Direction Port A Bit 4
DDRA_BIT5: equ 5 ; Data Direction Port A Bit 5
DDRA_BIT6: equ 6 ; Data Direction Port A Bit 6
DDRA_BIT7: equ 7 ; Data Direction Port A Bit 7
; bit position masks
mDDRA_BIT0: equ %00000001
mDDRA_BIT1: equ %00000010
mDDRA_BIT2: equ %00000100
mDDRA_BIT3: equ %00001000
mDDRA_BIT4: equ %00010000
mDDRA_BIT5: equ %00100000
mDDRA_BIT6: equ %01000000
mDDRA_BIT7: equ %10000000
;*** DDRB - Port B Data Direction Register; 0x00000003 ***
DDRB: equ $00000003 ;*** DDRB - Port B Data Direction Register; 0x00000003 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRB_BIT0: equ 0 ; Data Direction Port B Bit 0
DDRB_BIT1: equ 1 ; Data Direction Port B Bit 1
DDRB_BIT2: equ 2 ; Data Direction Port B Bit 2
DDRB_BIT3: equ 3 ; Data Direction Port B Bit 3
DDRB_BIT4: equ 4 ; Data Direction Port B Bit 4
DDRB_BIT5: equ 5 ; Data Direction Port B Bit 5
DDRB_BIT6: equ 6 ; Data Direction Port B Bit 6
DDRB_BIT7: equ 7 ; Data Direction Port B Bit 7
; bit position masks
mDDRB_BIT0: equ %00000001
mDDRB_BIT1: equ %00000010
mDDRB_BIT2: equ %00000100
mDDRB_BIT3: equ %00001000
mDDRB_BIT4: equ %00010000
mDDRB_BIT5: equ %00100000
mDDRB_BIT6: equ %01000000
mDDRB_BIT7: equ %10000000
;*** PORTE - Port E Register; 0x00000008 ***
PORTE: equ $00000008 ;*** PORTE - Port E Register; 0x00000008 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTE_BIT0: equ 0 ; Port E Bit 0
PORTE_BIT1: equ 1 ; Port E Bit 1
PORTE_BIT2: equ 2 ; Port E Bit 2
PORTE_BIT3: equ 3 ; Port E Bit 3
PORTE_BIT4: equ 4 ; Port E Bit 4
PORTE_BIT5: equ 5 ; Port E Bit 5
PORTE_BIT6: equ 6 ; Port E Bit 6
PORTE_BIT7: equ 7 ; Port E Bit 7
; bit position masks
mPORTE_BIT0: equ %00000001
mPORTE_BIT1: equ %00000010
mPORTE_BIT2: equ %00000100
mPORTE_BIT3: equ %00001000
mPORTE_BIT4: equ %00010000
mPORTE_BIT5: equ %00100000
mPORTE_BIT6: equ %01000000
mPORTE_BIT7: equ %10000000
;*** DDRE - Port E Data Direction Register; 0x00000009 ***
DDRE: equ $00000009 ;*** DDRE - Port E Data Direction Register; 0x00000009 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRE_BIT2: equ 2 ; Data Direction Port E Bit 2
DDRE_BIT3: equ 3 ; Data Direction Port E Bit 3
DDRE_BIT4: equ 4 ; Data Direction Port E Bit 4
DDRE_BIT5: equ 5 ; Data Direction Port E Bit 5
DDRE_BIT6: equ 6 ; Data Direction Port E Bit 6
DDRE_BIT7: equ 7 ; Data Direction Port E Bit 7
; bit position masks
mDDRE_BIT2: equ %00000100
mDDRE_BIT3: equ %00001000
mDDRE_BIT4: equ %00010000
mDDRE_BIT5: equ %00100000
mDDRE_BIT6: equ %01000000
mDDRE_BIT7: equ %10000000
;*** PEAR - Port E Assignment Register; 0x0000000A ***
PEAR: equ $0000000A ;*** PEAR - Port E Assignment Register; 0x0000000A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PEAR_RDWE: equ 2 ; Read / Write Enable
PEAR_LSTRE: equ 3 ; Low Strobe (LSTRB) Enable
PEAR_NECLK: equ 4 ; No External E Clock
PEAR_PIPOE: equ 5 ; Pipe Status Signal Output Enable
PEAR_NOACCE: equ 7 ; CPU No Access Output Enable
; bit position masks
mPEAR_RDWE: equ %00000100
mPEAR_LSTRE: equ %00001000
mPEAR_NECLK: equ %00010000
mPEAR_PIPOE: equ %00100000
mPEAR_NOACCE: equ %10000000
;*** MODE - Mode Register; 0x0000000B ***
MODE: equ $0000000B ;*** MODE - Mode Register; 0x0000000B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MODE_EME: equ 0 ; Emulate Port E
MODE_EMK: equ 1 ; Emulate Port K
MODE_IVIS: equ 3 ; Internal Visibility
MODE_MODA: equ 5 ; Mode Select Bit A
MODE_MODB: equ 6 ; Mode Select Bit B
MODE_MODC: equ 7 ; Mode Select Bit C
; bit position masks
mMODE_EME: equ %00000001
mMODE_EMK: equ %00000010
mMODE_IVIS: equ %00001000
mMODE_MODA: equ %00100000
mMODE_MODB: equ %01000000
mMODE_MODC: equ %10000000
;*** PUCR - Pull-Up Control Register; 0x0000000C ***
PUCR: equ $0000000C ;*** PUCR - Pull-Up Control Register; 0x0000000C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PUCR_PUPAE: equ 0 ; Pull-Up Port A Enable
PUCR_PUPBE: equ 1 ; Pull-Up Port B Enable
PUCR_PUPEE: equ 4 ; Pull-Up Port E Enable
PUCR_PUPKE: equ 7 ; Pull-Up Port K Enable
; bit position masks
mPUCR_PUPAE: equ %00000001
mPUCR_PUPBE: equ %00000010
mPUCR_PUPEE: equ %00010000
mPUCR_PUPKE: equ %10000000
;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
RDRIV: equ $0000000D ;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
RDRIV_RDPA: equ 0 ; Reduced Drive of Port A
RDRIV_RDPB: equ 1 ; Reduced Drive of Port B
RDRIV_RDPE: equ 4 ; Reduced Drive of Port E
RDRIV_RDPK: equ 7 ; Reduced Drive of Port K
; bit position masks
mRDRIV_RDPA: equ %00000001
mRDRIV_RDPB: equ %00000010
mRDRIV_RDPE: equ %00010000
mRDRIV_RDPK: equ %10000000
;*** EBICTL - External Bus Interface Control; 0x0000000E ***
EBICTL: equ $0000000E ;*** EBICTL - External Bus Interface Control; 0x0000000E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
EBICTL_ESTR: equ 0 ; E Stretches
; bit position masks
mEBICTL_ESTR: equ %00000001
;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
INITRM: equ $00000010 ;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INITRM_RAMHAL: equ 0 ; Internal RAM map alignment
INITRM_RAM11: equ 3 ; Internal RAM map position Bit 11
INITRM_RAM12: equ 4 ; Internal RAM map position Bit 12
INITRM_RAM13: equ 5 ; Internal RAM map position Bit 13
INITRM_RAM14: equ 6 ; Internal RAM map position Bit 14
INITRM_RAM15: equ 7 ; Internal RAM map position Bit 15
; bit position masks
mINITRM_RAMHAL: equ %00000001
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