📄 main.dbg
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;**************************************************************
;* This stationery serves as the framework for a *
;* user application. For a more comprehensive program that *
;* demonstrates the more advanced functionality of this *
;* processor, please see the demonstration applications *
;* located in the examples subdirectory of the *
;* Freescale CodeWarrior for the HC12 Program directory *
;**************************************************************
; export symbols
XDEF Entry, main
; we use export 'Entry' as symbol. This allows us to
; reference 'Entry' either in the linker .prm file
; or from C/C++ later on
XREF __SEG_END_SSTACK ; symbol defined by the linker for the end of the stack
; include derivative specific macros
INCLUDE 'mc9s12dg128.inc'
; Based on CPU DB MC9S12DG128_112, version 2.87.331 (RegistersPrg V2.09)
; ###################################################################
; Filename : mc9s12dg128.inc
; Processor : MC9S12DG128BCPV
; FileFormat: V2.09
; DataSheet : 9S12DT128BDGV1/D V01.05
; Compiler : CodeWarrior compiler
; Date/Time : 14.09.2006, 20:52
; Abstract :
; This header implements the mapping of I/O devices.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2006
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
;
; File-Format-Revisions:
; - 14.11.2005, V2.00 :
; - Deprecated symbols added for backward compatibility (section at the end of this file)
; - 15.11.2005, V2.01 :
; - Fixed invalid instruction in macro __RESET_WATCHDOG for HCS12 family.
; - 17.12.2005, V2.02 :
; - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
; - 16.01.2006, V2.03 :
; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
; - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
; - 08.03.2006, V2.04 :
; - Support for bit(s) names duplicated with any register name in .h header files
; - 24.03.2006, V2.05 :
; - Fixed macro __RESET_WATCHDOG for HCS12 family - address and correct write order.
; - 26.04.2006, V2.06 :
; - Revision is not related to this file (CPU family)
; - 27.04.2006, V2.07 :
; - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
; - 07.06.2006, V2.08 :
; - Revision is not related to this file (CPU family)
; - 03.07.2006, V2.09 :
; - Revision is not related to this file (CPU family)
;
; CPU Registers Revisions:
; - 24.05.2006, V2.87.287:
; - Removed bits MCCNTlo_BIT0..MCCNTlo_BIT7 and MCCNThi_BIT8.. MCCNThi_BIT15. REASON: Bug-fix (#3166 from UNIS issue manager)
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
RAMStart: equ $00000400
RAMEnd: equ $00001FFF
ROM_4000Start: equ $00004000
ROM_4000End: equ $00007FFF
ROM_C000Start: equ $0000C000
ROM_C000End: equ $0000FEFF
PAGE_38Start: equ $00388000
PAGE_38End: equ $0038BFFF
PAGE_39Start: equ $00398000
PAGE_39End: equ $0039BFFF
PAGE_3AStart: equ $003A8000
PAGE_3AEnd: equ $003ABFFF
PAGE_3BStart: equ $003B8000
PAGE_3BEnd: equ $003BBFFF
PAGE_3CStart: equ $003C8000
PAGE_3CEnd: equ $003CBFFF
PAGE_3DStart: equ $003D8000
PAGE_3DEnd: equ $003DBFFF
;
VReserved63: equ $0000FF80
VReserved62: equ $0000FF82
VReserved61: equ $0000FF84
VReserved60: equ $0000FF86
VReserved59: equ $0000FF88
VReserved58: equ $0000FF8A
Vpwmesdn: equ $0000FF8C
Vportp: equ $0000FF8E
Vcan4tx: equ $0000FF90
Vcan4rx: equ $0000FF92
Vcan4err: equ $0000FF94
Vcan4wkup: equ $0000FF96
VReserved51: equ $0000FF98
VReserved50: equ $0000FF9A
VReserved49: equ $0000FF9C
VReserved48: equ $0000FF9E
VReserved47: equ $0000FFA0
VReserved46: equ $0000FFA2
VReserved45: equ $0000FFA4
VReserved44: equ $0000FFA6
VReserved43: equ $0000FFA8
VReserved42: equ $0000FFAA
VReserved41: equ $0000FFAC
VReserved40: equ $0000FFAE
Vcan0tx: equ $0000FFB0
Vcan0rx: equ $0000FFB2
Vcan0err: equ $0000FFB4
Vcan0wkup: equ $0000FFB6
Vflash: equ $0000FFB8
Veeprom: equ $0000FFBA
VReserved33: equ $0000FFBC
Vspi1: equ $0000FFBE
Viic: equ $0000FFC0
VReserved30: equ $0000FFC2
Vcrgscm: equ $0000FFC4
Vcrgplllck: equ $0000FFC6
Vtimpabovf: equ $0000FFC8
Vtimmdcu: equ $0000FFCA
Vporth: equ $0000FFCC
Vportj: equ $0000FFCE
Vatd1: equ $0000FFD0
Vatd0: equ $0000FFD2
Vsci1: equ $0000FFD4
Vsci0: equ $0000FFD6
Vspi0: equ $0000FFD8
Vtimpaie: equ $0000FFDA
Vtimpaaovf: equ $0000FFDC
Vtimovf: equ $0000FFDE
Vtimch7: equ $0000FFE0
Vtimch6: equ $0000FFE2
Vtimch5: equ $0000FFE4
Vtimch4: equ $0000FFE6
Vtimch3: equ $0000FFE8
Vtimch2: equ $0000FFEA
Vtimch1: equ $0000FFEC
Vtimch0: equ $0000FFEE
Vrti: equ $0000FFF0
Virq: equ $0000FFF2
Vxirq: equ $0000FFF4
Vswi: equ $0000FFF6
Vtrap: equ $0000FFF8
Vcop: equ $0000FFFA
Vclkmon: equ $0000FFFC
Vreset: equ $0000FFFE
;
;*** PORTAB - Port AB Register; 0x00000000 ***
PORTAB: equ $00000000 ;*** PORTAB - Port AB Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTAB_BIT0: equ 0 ; Port AB Bit 0
PORTAB_BIT1: equ 1 ; Port AB Bit 1
PORTAB_BIT2: equ 2 ; Port AB Bit 2
PORTAB_BIT3: equ 3 ; Port AB Bit 3
PORTAB_BIT4: equ 4 ; Port AB Bit 4
PORTAB_BIT5: equ 5 ; Port AB Bit 5
PORTAB_BIT6: equ 6 ; Port AB Bit 6
PORTAB_BIT7: equ 7 ; Port AB Bit 7
PORTAB_BIT8: equ 8 ; Port AB Bit 8
PORTAB_BIT9: equ 9 ; Port AB Bit 9
PORTAB_BIT10: equ 10 ; Port AB Bit 10
PORTAB_BIT11: equ 11 ; Port AB Bit 11
PORTAB_BIT12: equ 12 ; Port AB Bit 12
PORTAB_BIT13: equ 13 ; Port AB Bit 13
PORTAB_BIT14: equ 14 ; Port AB Bit 14
PORTAB_BIT15: equ 15 ; Port AB Bit 15
; bit position masks
mPORTAB_BIT0: equ %00000001
mPORTAB_BIT1: equ %00000010
mPORTAB_BIT2: equ %00000100
mPORTAB_BIT3: equ %00001000
mPORTAB_BIT4: equ %00010000
mPORTAB_BIT5: equ %00100000
mPORTAB_BIT6: equ %01000000
mPORTAB_BIT7: equ %10000000
mPORTAB_BIT8: equ %100000000
mPORTAB_BIT9: equ %1000000000
mPORTAB_BIT10: equ %10000000000
mPORTAB_BIT11: equ %100000000000
mPORTAB_BIT12: equ %1000000000000
mPORTAB_BIT13: equ %10000000000000
mPORTAB_BIT14: equ %100000000000000
mPORTAB_BIT15: equ %1000000000000000
;*** PORTA - Port A Register; 0x00000000 ***
PORTA: equ $00000000 ;*** PORTA - Port A Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTA_BIT0: equ 0 ; Port A Bit 0
PORTA_BIT1: equ 1 ; Port A Bit 1
PORTA_BIT2: equ 2 ; Port A Bit 2
PORTA_BIT3: equ 3 ; Port A Bit 3
PORTA_BIT4: equ 4 ; Port A Bit 4
PORTA_BIT5: equ 5 ; Port A Bit 5
PORTA_BIT6: equ 6 ; Port A Bit 6
PORTA_BIT7: equ 7 ; Port A Bit 7
; bit position masks
mPORTA_BIT0: equ %00000001
mPORTA_BIT1: equ %00000010
mPORTA_BIT2: equ %00000100
mPORTA_BIT3: equ %00001000
mPORTA_BIT4: equ %00010000
mPORTA_BIT5: equ %00100000
mPORTA_BIT6: equ %01000000
mPORTA_BIT7: equ %10000000
;*** PORTB - Port B Register; 0x00000001 ***
PORTB: equ $00000001 ;*** PORTB - Port B Register; 0x00000001 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PORTB_BIT0: equ 0 ; Port B Bit 0
PORTB_BIT1: equ 1 ; Port B Bit 1
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