mx1_def.h

Linux s3c2410键盘驱动源码

#define PTC_OCR2                (PTC_BASE_ADDR+0x08)                
#define PTC_ICONFA1             (PTC_BASE_ADDR+0x0C)                
#define PTC_ICONFA2             (PTC_BASE_ADDR+0x10)                
#define PTC_ICONFB1             (PTC_BASE_ADDR+0x14)                
#define PTC_ICONFB2             (PTC_BASE_ADDR+0x18)                
#define PTC_DR                  (PTC_BASE_ADDR+0x1C)                
#define PTC_GIUS                (PTC_BASE_ADDR+0x20)                
#define PTC_SSR                 (PTC_BASE_ADDR+0x24)                
#define PTC_ICR1                (PTC_BASE_ADDR+0x28)                
#define PTC_ICR2                (PTC_BASE_ADDR+0x2C)                
#define PTC_IMR                 (PTC_BASE_ADDR+0x30)                
#define PTC_ISR                 (PTC_BASE_ADDR+0x34)                
#define PTC_GPR                 (PTC_BASE_ADDR+0x38)                
#define PTC_SWR                 (PTC_BASE_ADDR+0x3C)                
#define PTC_PUEN                (PTC_BASE_ADDR+0x40)                

// ;---------------------------------------;
// ; GPIO - PTD                            ;
// ; $0021_C300 to $0021_C3FF              ;
// ;---------------------------------------;
#define PTD_BASE_ADDR           0xf021C300                
#define PTD_DDIR                PTD_BASE_ADDR                
#define PTD_OCR1                (PTD_BASE_ADDR+0x04)                
#define PTD_OCR2                (PTD_BASE_ADDR+0x08)                
#define PTD_ICONFA1             (PTD_BASE_ADDR+0x0C)                
#define PTD_ICONFA2             (PTD_BASE_ADDR+0x10)                
#define PTD_ICONFB1             (PTD_BASE_ADDR+0x14)                
#define PTD_ICONFB2             (PTD_BASE_ADDR+0x18)                
#define PTD_DR                  (PTD_BASE_ADDR+0x1C)                
#define PTD_GIUS                (PTD_BASE_ADDR+0x20)                
#define PTD_SSR                 (PTD_BASE_ADDR+0x24)                
#define PTD_ICR1                (PTD_BASE_ADDR+0x28)                
#define PTD_ICR2                (PTD_BASE_ADDR+0x2C)                
#define PTD_IMR                 (PTD_BASE_ADDR+0x30)                
#define PTD_ISR                 (PTD_BASE_ADDR+0x34)                
#define PTD_GPR                 (PTD_BASE_ADDR+0x38)                
#define PTD_SWR                 (PTD_BASE_ADDR+0x3C)                
#define PTD_PUEN                (PTD_BASE_ADDR+0x40) 
//
// ;---------------------------------------;
// ; LCDC                                  ;
// ; $0020_5000 to $0020_5FFF              ;
// ;---------------------------------------;
#define LCDC_BASE_ADDR          0xf0205000                
#define LCDC_PAL_ADDR           0xf0205800                
#define LCDC_ssa                LCDC_BASE_ADDR                
#define LCDC_xymax              (LCDC_BASE_ADDR+0x04)                
#define LCDC_vpw                (LCDC_BASE_ADDR+0x08)                
#define LCDC_hcc_xy             (LCDC_BASE_ADDR+0x0C)                
#define LCDC_hcc_w              (LCDC_BASE_ADDR+0x10)                
#define LCDC_chcc               (LCDC_BASE_ADDR+0x14)                
#define LCDC_con                (LCDC_BASE_ADDR+0x18)                
#define LCDC_hsyn               (LCDC_BASE_ADDR+0x1C)                
#define LCDC_vsyn               (LCDC_BASE_ADDR+0x20)                
#define LCDC_pan                (LCDC_BASE_ADDR+0x24)                
#define LCDC_gpm                (LCDC_BASE_ADDR+0x28)                
#define LCDC_pwm                (LCDC_BASE_ADDR+0x2C)                
#define LCDC_dma                (LCDC_BASE_ADDR+0x30)                
#define LCDC_self               (LCDC_BASE_ADDR+0x34)                
#define LCDC_int                (LCDC_BASE_ADDR+0x38)                
#define LCDC_status             (LCDC_BASE_ADDR+0x40)                
#define LCDC_ram_0              LCDC_PAL_ADDR
#define LCDC_ram_1              (LCDC_PAL_ADDR+0x04)                
#define LCDC_ram_2              (LCDC_PAL_ADDR+0x08)                
#define LCDC_ram_3              (LCDC_PAL_ADDR+0x0C)                
#define LCDC_ram_4              (LCDC_PAL_ADDR+0x10)                
#define LCDC_ram_5              (LCDC_PAL_ADDR+0x14)                
#define LCDC_ram_6              (LCDC_PAL_ADDR+0x18)                
#define LCDC_ram_7              (LCDC_PAL_ADDR+0x1C)                
#define LCDC_ram_8              (LCDC_PAL_ADDR+0x20)                
#define LCDC_ram_9              (LCDC_PAL_ADDR+0x24)                
#define LCDC_ram_a              (LCDC_PAL_ADDR+0x28)                
#define LCDC_ram_b              (LCDC_PAL_ADDR+0x2C)                
#define LCDC_ram_c              (LCDC_PAL_ADDR+0x30)                
#define LCDC_ram_d              (LCDC_PAL_ADDR+0x34)                
#define LCDC_ram_e              (LCDC_PAL_ADDR+0x38)                
#define LCDC_ram_f              (LCDC_PAL_ADDR+0x3c) 
//
// ;---------------------------------------;
// ; I2C                                   ;
// ; $0021_7000 to $0021_7FFF              ;
// ;---------------------------------------;
//
#define I2C_BASE_ADDR           0xf0217000 
#define I2C_IADR                I2C_BASE_ADDR 
#define I2C_IFDR                (I2C_BASE_ADDR+0x04)
#define I2C_I2CR                (I2C_BASE_ADDR+0x08)
#define I2C_I2SR                (I2C_BASE_ADDR+0x0C) 
#define I2C_I2DR                (I2C_BASE_ADDR+0x10) 
//
// ;---------------------------------------;
// ; SSI                                   ;
// ; $0021_8000 to $0021_8FFF              ;
// ;---------------------------------------;
#define SSI_BASE_ADDR           0xf0218000                
#define SSI_STX                 SSI_BASE_ADDR                
#define SSI_SRX                 (SSI_BASE_ADDR+0x04)                
#define SSI_SCSR                (SSI_BASE_ADDR+0x08) 
#define SSI_STCR                (SSI_BASE_ADDR+0x0C)   
#define SSI_SRCR                (SSI_BASE_ADDR+0x10)               
#define SSI_STCCR               (SSI_BASE_ADDR+0x14)                
#define SSI_SRCCR               (SSI_BASE_ADDR+0x18)                
#define SSI_STSR                (SSI_BASE_ADDR+0x1C)               
#define SSI_SFCSR               (SSI_BASE_ADDR+0x20)                
#define SSI_STR                 (SSI_BASE_ADDR+0x24)                
#define SSI_SOR                 (SSI_BASE_ADDR+0x28)                    
//
// ;---------------------------------------;
// ; MMC all the address used for SDHC     ;
// ; $0021_4000 to $0021_4FFF              ;
// ;---------------------------------------;
//
#define MMC_BASE_ADDR           0xf0214000                
#define MMC_STR_STP_CLK         MMC_BASE_ADDR                
#define MMC_STATUS              (MMC_BASE_ADDR+0x04)
#define MMC_CLK_RATE            (MMC_BASE_ADDR+0x08)
#define MMC_CMD_DAT_CONT        (MMC_BASE_ADDR+0x0C)
#define MMC_RESPONSE_TO         (MMC_BASE_ADDR+0x10)
#define MMC_READ_TO             (MMC_BASE_ADDR+0x14)                
#define MMC_BLK_LEN             (MMC_BASE_ADDR+0x18)                
#define MMC_NOB                 (MMC_BASE_ADDR+0x1C)                
#define MMC_REV_NO              (MMC_BASE_ADDR+0x20)                
#define MMC_INT_MASK            (MMC_BASE_ADDR+0x24)
#define MMC_CMD                 (MMC_BASE_ADDR+0x28)
#define MMC_ARGH                (MMC_BASE_ADDR+0x2C)
#define MMC_ARGL                (MMC_BASE_ADDR+0x30)
#define MMC_RES_FIFO            (MMC_BASE_ADDR+0x34)                
#define MMC_BUFFER_ACCESS       (MMC_BASE_ADDR+0x38)                
#define MMC_BUF_PART_FULL       (MMC_BASE_ADDR+0x3C)  
#define MMC_OTHERS_REGS_1       (MMC_BASE_ADDR+0x40)  
#define MMC_OTHERS_REGS_2       (MMC_BASE_ADDR+0x80)  
#define MMC_OTHERS_REGS_3       (MMC_BASE_ADDR+0x100)  
#define MMC_OTHERS_REGS_4       (MMC_BASE_ADDR+0x200)  
#define MMC_OTHERS_REGS_5       (MMC_BASE_ADDR+0x400)  
#define MMC_OTHERS_REGS_6       (MMC_BASE_ADDR+0x800)  
//
// ;---------------------------------------;
// ; MSHC                                  ;
// ; $0021_A000 to $0021_AFFF              ;
// ;---------------------------------------;
#define MSHC_BASE_ADDR          0xf021A000
#define MSHC_MSCMD              MSHC_BASE_ADDR                  // ; Command Reg
#define MSHC_MSCS               (MSHC_BASE_ADDR+0x02)   // ; Control/Status Reg
#define MSHC_MSDATA             (MSHC_BASE_ADDR+0x04)   // ; Tx/Rx FIFO Reg
#define MSHC_MSICS              (MSHC_BASE_ADDR+0x06)   // ; Interrupt Control/Status Reg
#define MSHC_MSPPCD             (MSHC_BASE_ADDR+0x08)   // ; Parallel Port Control/Data Reg
#define MSHC_MSC2               (MSHC_BASE_ADDR+0x0A)   // ; Control2 Reg
#define MSHC_MSACMD             (MSHC_BASE_ADDR+0x0C)   // ; Auto Command Reg
#define MSHC_MSFAECS            (MSHC_BASE_ADDR+0x0E)   // ; FIFO Acc Err Ctrl/Status Reg
#define MSHC_MSCLKD             (MSHC_BASE_ADDR+0x10)   // ; Serial Clock Div Control Reg
#define MSHC_MSDRQC             (MSHC_BASE_ADDR+0x12)   // ; DMA Request Control Reg
//
// ;---------------------------------------;
// ; PORTHOLE                              ;
// ;---------------------------------------;
#define EVENT_PORTHOLE          0x12301000  // ; User Event Porthole
#define EVENT_PH                0x12301000
#define EVENT                   0x12301000
#define PASS_PORTHOLE           0x12301004
#define PASS_PH                 0x12301004
#define FAIL_PORTHOLE           0x12301008
#define FAIL_PH                 0x12301008
#define STOP_PORTHOLE           0x1230100C
#define STOP_PH                 0x1230100C
#define FINISH_PORTHOLE         0x12301010
#define FINISH_PH               0x12301010
//
#define EXP_DATA_PH             0x12301014
#define CODE_DATA_PH            0x12301018
#define ADDR_DATA_PH            0x1230101C
#define ACT_DATA_PH             0x12301020
//
#define EVENT_VALUE             0x0000beef  // ; Code execution complete trigger
#define USER_EVENT0_DATA        0xbadbeef0
#define USER_EVENT1_DATA        0xbadbeef1
#define USER_EVENT2_DATA        0xbadbeef2
#define USER_EVENT3_DATA        0xbadbeef3
#define USER_EVENT4_DATA        0xbadbeef4
#define USER_EVENT5_DATA        0xbadbeef5
#define USER_EVENT6_DATA        0xbadbeef6
#define USER_EVENT7_DATA        0xbadbeef7
#define USER_EVENT8_DATA        0xbadbeef8
#define USER_EVENT9_DATA        0xbadbeef9
#define USER_EVENT10_DATA       0xbadbeefa
#define USER_EVENT11_DATA       0xbadbeefb
#define USER_EVENT12_DATA       0xbadbeefc
#define USER_EVENT13_DATA       0xbadbeefd
#define USER_EVENT14_DATA       0xbadbeefe
#define USER_EVENT15_DATA       0xbadbeeff
#define MCU_JNT_HALT            0xdeaddead
//
// ;---------------------------------------;
// ; PWM                                   ;
// ; $0020_8000 to $0020_8FFF              ;
// ;---------------------------------------;
#define PWM1_BASE_ADDR          0xf0208000                
#define PWMC1                   PWM1_BASE_ADDR                
#define PWMS1                   (PWM1_BASE_ADDR+0x04)                
#define PWMP1                   (PWM1_BASE_ADDR+0x08)                
#define PWMCNT1                 (PWM1_BASE_ADDR+0x0C)                
#define PWMTST1                 (PWM1_BASE_ADDR+0x10)                

// ;---------------------------------------;
// ; RAM                 Karen moved                       ;
// ; $0030_0100 to $0031_FFFF              ;
// ; $0030_0000 to $0030_00FF for PORTHOLE ;
// ;---------------------------------------;
//#define RAM1_BASE_ADDR          0xf0300100
//#define RAM1_END_ADDR           (RAM1_BASE_ADDR+0x0FF00)
//#define RAM2_BASE_ADDR          0xf0310000
//#define RAM2_END_ADDR           (RAM2_BASE_ADDR+0x10000)
//#define TOP_OF_STACK            0xf0320000
//
// ;---------------------------------------;
// ; RTC                                   ;
// ; $0020_4000 to $0020_4FFF              ;
// ;---------------------------------------;
#define RTC_BASE_ADDR           0xf0204000                
#define RTC_HOURMIN             RTC_BASE_ADDR                
#define RTC_SECOND              (RTC_BASE_ADDR+0x04)                
#define RTC_ALRM_HM             (RTC_BASE_ADDR+0x08)                
#define RTC_ALRM_SEC            (RTC_BASE_ADDR+0x0C)                
#define RTC_RTCCTL              (RTC_BASE_ADDR+0x10)                
#define RTC_RTCISR              (RTC_BASE_ADDR+0x14)                
#define RTC_RTCIENR             (RTC_BASE_ADDR+0x18)                
#define RTC_STPWCH              (RTC_BASE_ADDR+0x1C)                
#define RTC_DAYR                (RTC_BASE_ADDR+0x20)                
#define RTC_DAYALARM            (RTC_BASE_ADDR+0x24)                
#define RTC_TEST1               (RTC_BASE_ADDR+0x28)                
#define RTC_TEST2               (RTC_BASE_ADDR+0x2C)                
#define RTC_TEST3               (RTC_BASE_ADDR+0x30)
//
// ;---------------------------------------;
// ; SRAMC                                 ;
// ; $0022_1000 to $0022_1FFF              ;
// ;---------------------------------------;
#define SDRAMC_BASE_ADDR        0xf0221000                
#define SDRAMC_SDCTL0           SDRAMC_BASE_ADDR                
#define SDRAMC_SDCTL1           (SDRAMC_BASE_ADDR+0x04)              
//
// ;---------------------------------------;
// ; SIM                                   ;
// ; $0021_1000 to $0021_21FF              ;
// ;---------------------------------------;
#define SIM_BASE_ADDR           0xf0211000                
#define SIM_PORT_CNTL           SIM_BASE_ADDR