📄 main.c
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//------------------------------------------------------------------------------
// Jai Shree-Krishna
//Project created on 9th Feb 09 by Chandrakant for Starter kit.
//RTC Tested Successfully on 120209.
//Wachdog Tested Successfully on 130209.
//UART completed with interrupt on receive char tested succesfully on 190209.
//------------------------------------------------------------------------------
//include
#include "includes.h"
//------------------------------------------------------------------------------
//defines
volatile unsigned int DlyCount;
//------------------------------------------------------------------------------
//variables
//------------------------------------------------------------------------------
// Function Name: Dly100us
// Parameters: void *arg
// Return: none
// Description: Delay 100us * arg
//------------------------------------------------------------------------------
void Dly100us(void *arg)
{
DlyCount = (Int32U)arg;
// Clear TIM0 counter
TIM_CounterCmd(TIM0, TIM_CLEAR);
// Clear TIM0 flag OC1
TIM_ClearFlag(TIM0,TIM_FLAG_OC1);
// Enable TIM0 OC1 interrupt
TIM_ITConfig(TIM0, TIM_IT_OC1, ENABLE);
// Enable TIM0 counter
TIM_CounterCmd(TIM0, TIM_START);
while(DlyCount);
// Disable TIM0 OC1 interrupt
TIM_ITConfig(TIM0, TIM_IT_OC1, DISABLE);
// Disable TIM0 counter
TIM_CounterCmd(TIM0, TIM_STOP);
}
//------------------------------------------------------------------------------
// Function Name: InitClock
// Parameters: none
// Return: none
// Description: Init MCU clock
//------------------------------------------------------------------------------
void InitClock (void)
{
// Clock
SCU_MCLKSourceConfig(SCU_MCLK_OSC); // master clk = OSC clk
// Flash controller init
SCU_FMICLKDivisorConfig(SCU_FMICLK_Div1);
FMI_Config(FMI_READ_WAIT_STATE_2,FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE,\
FMI_LVD_ENABLE,FMI_FREQ_HIGH);
// Set clks dividers
SCU_RCLKDivisorConfig(SCU_RCLK_Div1);
SCU_HCLKDivisorConfig(SCU_HCLK_Div1);
SCU_PCLKDivisorConfig(SCU_PCLK_Div1);
// Init PLL = 48 MHz
SCU_PLLFactorsConfig(192,25,2);
// PLL Enabled
SCU_PLLCmd(ENABLE);
// Switch clk MCLK = PLL
SCU_MCLKSourceConfig(SCU_MCLK_PLL);
}
//------------------------------------------------------------------------------
// Function Name: InitTimer0
// Parameters: Int32U IntrPriority
// Return: none
// Description: Init Timer (TIM 0)
//------------------------------------------------------------------------------
void InitTimer0 (Int32U IntrPriority)
{
TIM_InitTypeDef TIM_InitStructure;
// Enable TIM0 clocks
SCU_APBPeriphClockConfig(__TIM01, ENABLE);
// Release TIM0 reset
SCU_APBPeriphReset(__TIM01,DISABLE);
// Timer 0
// TIM Configuration in Output Compare Timing Mode period 100us
TIM_InitStructure.TIM_Mode = TIM_OCM_CHANNEL_1; // OUTPUT COMPARE CHANNEL 1 Mode
TIM_InitStructure.TIM_OC1_Modes = TIM_TIMING; // OCMP1 pin is disabled
TIM_InitStructure.TIM_Clock_Source = TIM_CLK_APB; // assign PCLK to TIM_Clk
TIM_InitStructure.TIM_Prescaler = 95; //48 - 1; // 1us resolution
TIM_InitStructure.TIM_Pulse_Length_1 = 10000; // 10ms
// TIM_InitStructure.TIM_Prescaler = 191; //95; //48 - 1; // 2us resolution
// TIM_InitStructure.TIM_Pulse_Length_1 = 50000; // 100ms
TIM_Init(TIM0, &TIM_InitStructure);
// VIC configuration
VIC_Config(TIM0_ITLine, VIC_IRQ, IntrPriority);
VIC_ITCmd(TIM0_ITLine, ENABLE);
//240309-->>
TIM_CounterCmd(TIM0, TIM_CLEAR);
// Clear TIM0 flag OC1
TIM_ClearFlag(TIM0,TIM_FLAG_OC1);
// Enable TIM0 OC1 interrupt
TIM_ITConfig(TIM0, TIM_IT_OC1, ENABLE);
// Enable TIM0 counter
//240309--<< */
}
//------------------------------------------------------------------------------
// Function Name: main
// Parameters : None
// Return : None
// Description : main function
//------------------------------------------------------------------------------
void main(void)
{
InitClock();
InitDisplay();
// Enable the clock for the VICs
SCU_AHBPeriphClockConfig(__VIC, ENABLE);
// VIC Deinitialization
VIC_DeInit();
// Delay timer init
InitTimer0(2);
//startup();
DrawScreen();
while(1);
}
//------------------------------------------------------------------------------
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