📄 hardware.lst
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// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
0000AAC2 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
0000AAC3 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
0000AAC5 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000AAC6 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
0000AAC8 09 93 00 FD R1 = 0xfd00 // 16K
0000AACA 19 D3 0A 70 [P_TimerA_Data] = R1
0000AACC 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
0000AACE 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000AAD0 09 93 FF FF R1 = 0xffff
0000AAD2 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000AAD4 40 92 R1 =0x0000 //
0000AAD5 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AAD7 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
0000AAD9 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AADB 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AADD 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
0000AADE 40 92 R1 = 0x0000 // 24MHz Fosc
0000AADF 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
0000AAE1 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000AAE2 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
0000AAE4 09 93 ED FC R1 = 0xfced // 15.625K
0000AAE6 19 D3 0A 70 [P_TimerA_Data]=R1
0000AAE8 09 93 A8 00 R1 = 0x00A8 //
0000AAEA 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
0000AAEC 09 93 FF FF R1 = 0xffff
0000AAEE 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000AAF0 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AAF2 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
0000AAF4 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AAF6 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AAF8 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000AAF9 60 92 R1=0x0020;
0000AAFA 19 D3 13 70 [P_SystemClock]=R1
0000AAFC 09 93 A8 00 R1 = 0x00A8; //
0000AAFE 19 D3 2A 70 [P_DAC_Ctrl]= R1
0000AB00 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000AB01 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
0000AB03 09 93 00 FE R1 = 0xfe00; // 24K
0000AB05 19 D3 0A 70 [P_TimerA_Data] = R1;
0000AB07 09 93 FF FF R1 = 0xffff
0000AB09 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000AB0B 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AB0D 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
0000AB0F 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AB11 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AB13 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
0000AB14 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
0000AB15 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
0000AB17 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000AB18 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
0000AB1A 40 92 R1 = 0x0000 // Fosc/2
0000AB1B 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
0000AB1D 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
0000AB1F 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
0000AB21 09 93 FF FF R1 = 0xffff
0000AB23 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000AB25 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
0000AB26 46 92 R1 = 0x0006
0000AB27 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000AB29 09 93 00 FE R1 = 0xFE00
0000AB2B 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000AB2D 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AB2F 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
0000AB31 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AB33 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AB35 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
0000AB36 09 93 A8 00 R1 = 0x00A8
0000AB38 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000AB3A 09 93 00 FE R1 = 0xFE00
0000AB3C 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000AB3E 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AB40 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000AB42 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AB44 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AB46 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
0000AB47 09 93 A8 00 R1 = 0x00A8
0000AB49 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000AB4B 09 93 9A FD R1 = 0xFD9A
0000AB4D 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000AB4F 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AB51 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000AB53 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AB55 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AB57 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
0000AB58 09 93 A8 00 R1 = 0x00A8
0000AB5A 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000AB5C 09 93 00 FD R1 = 0xFD00
0000AB5E 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000AB60 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AB62 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000AB64 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AB66 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AB68 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
0000AB69 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000AB6A 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000AB6C 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000AB6D 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000AB6F 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
0000AB71 19 D3 0A 70 [P_TimerA_Data] = r1;
0000AB73 75 92 r1 = 0x0035; // ADINI should be open (107)
0000AB74 19 D3 15 70 [P_ADC_Ctrl] = r1;
0000AB76 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
0000AB78 19 D3 2A 70 [P_DAC_Ctrl] = r1;
0000AB7A 09 93 FF FF r1 = 0xffff;
0000AB7C 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
0000AB7E 11 93 4E 04 R1 = [R_InterruptStatus] //
0000AB80 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
0000AB82 19 D3 4E 04 [R_InterruptStatus] = R1 //
0000AB84 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000AB86 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
0000AB87 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
0000AB88 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
0000AB8A 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
0000AB8C 19 D3 0A 70 [P_TimerA_Data] = r1
0000AB8E 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
0000AB8F 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
0000AB90 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
0000AB92 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
0000AB94 19 D3 0A 70 [P_TimerA_Data] = r1;
0000AB96 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
0000AB97 90 D4 push r1,r2 to [sp]
0000AB98 11 93 17 70 r1=[P_DAC1]
0000AB9A 09 B3 C0 FF r1 &= ~0x003f
0000AB9C 09 43 00 80 cmp r1,0x8000
0000AB9E 0E 0E jb L_RU_NormalUp
0000AB9F 19 5E je L_RU_End
L_RU_DownLoop:
0000ABA0 40 F0 03 AC call F_Delay
0000ABA2 41 94 r2 = 0x0001
0000ABA3 1A D5 12 70 [P_Watchdog_Clear] = r2
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