📄 arm-options.html
字号:
<html lang="en"><head><title>Using the GNU Compiler Collection (GCC)</title><meta http-equiv="Content-Type" content="text/html"><meta name="description" content="Using the GNU Compiler Collection (GCC)"><meta name="generator" content="makeinfo 4.6"><!--Copyright © 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. <p>Permission is granted to copy, distribute and/or modify this documentunder the terms of the GNU Free Documentation License, Version 1.2 orany later version published by the Free Software Foundation; with theInvariant Sections being "GNU General Public License" and "FundingFree Software", the Front-Cover texts being (a) (see below), and withthe Back-Cover Texts being (b) (see below). A copy of the license isincluded in the section entitled "GNU Free Documentation License". <p>(a) The FSF's Front-Cover Text is: <p>A GNU Manual <p>(b) The FSF's Back-Cover Text is: <p>You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development.--><meta http-equiv="Content-Style-Type" content="text/css"><style type="text/css"><!-- pre.display { font-family:inherit } pre.format { font-family:inherit } pre.smalldisplay { font-family:inherit; font-size:smaller } pre.smallformat { font-family:inherit; font-size:smaller } pre.smallexample { font-size:smaller } pre.smalllisp { font-size:smaller }--></style></head><body><div class="node"><p>Node: <a name="ARM%20Options">ARM Options</a>,Next: <a rel="next" accesskey="n" href="MN10300-Options.html#MN10300%20Options">MN10300 Options</a>,Previous: <a rel="previous" accesskey="p" href="SPARC-Options.html#SPARC%20Options">SPARC Options</a>,Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel%20Options">Submodel Options</a><hr><br></div><h3 class="subsection">ARM Options</h4><p>These <code>-m</code> options are defined for Advanced RISC Machines (ARM)architectures: <dl><dt><code>-mabi=</code><var>name</var><code></code> <dd>Generate code for the specified ABI. Permissible values are: <code>apcs-gnu</code>,<code>atpcs</code>, <code>aapcs</code> and <code>iwmmxt</code>. <br><dt><code>-mapcs-frame</code> <dd>Generate a stack frame that is compliant with the ARM Procedure CallStandard for all functions, even if this is not strictly necessary forcorrect execution of the code. Specifying <code>-fomit-frame-pointer</code>with this option will cause the stack frames not to be generated forleaf functions. The default is <code>-mno-apcs-frame</code>. <br><dt><code>-mapcs</code> <dd>This is a synonym for <code>-mapcs-frame</code>. <br><dt><code>-mapcs-26</code> <dd>Generate code for a processor running with a 26-bit program counter,and conforming to the function calling standards for the APCS 26-bitoption. This option replaces the <code>-m2</code> and <code>-m3</code> optionsof previous releases of the compiler. <br><dt><code>-mapcs-32</code> <dd>Generate code for a processor running with a 32-bit program counter,and conforming to the function calling standards for the APCS 32-bitoption. This option replaces the <code>-m6</code> option of previous releasesof the compiler. <br><dt><code>-mthumb-interwork</code> <dd>Generate code which supports calling between the ARM and Thumbinstruction sets. Without this option the two instruction sets cannotbe reliably used inside one program. The default is<code>-mno-thumb-interwork</code>, since slightly larger code is generatedwhen <code>-mthumb-interwork</code> is specified. <br><dt><code>-mno-sched-prolog</code> <dd>Prevent the reordering of instructions in the function prolog, or themerging of those instruction with the instructions in the function'sbody. This means that all functions will start with a recognizable setof instructions (or in fact one of a choice from a small set ofdifferent function prologues), and this information can be used tolocate the start if functions inside an executable piece of code. Thedefault is <code>-msched-prolog</code>. <br><dt><code>-mhard-float</code> <dd>Generate output containing floating point instructions. This is thedefault. <br><dt><code>-msoft-float</code> <dd>Generate output containing library calls for floating point. <strong>Warning:</strong> the requisite libraries are not available for all ARMtargets. Normally the facilities of the machine's usual C compiler areused, but this cannot be done directly in cross-compilation. You must makeyour own arrangements to provide suitable library functions forcross-compilation. <p><code>-msoft-float</code> changes the calling convention in the output file;therefore, it is only useful if you compile <em>all</em> of a program withthis option. In particular, you need to compile <code>libgcc.a</code>, thelibrary that comes with GCC, with <code>-msoft-float</code> in order forthis to work. <br><dt><code>-mfloat-abi=</code><var>name</var><code></code> <dd>Specifies which ABI to use for floating point values. Permissible valuesare: <code>soft</code>, <code>softfp</code> and <code>hard</code>. <p><code>soft</code> and <code>hard</code> are equivalent to <code>-msoft-float</code>and <code>-mhard-float</code> respectively. <code>softfp</code> allows the generationof floating point instructions, but still uses the soft-float callingconventions. <br><dt><code>-mlittle-endian</code> <dd>Generate code for a processor running in little-endian mode. This isthe default for all standard configurations. <br><dt><code>-mbig-endian</code> <dd>Generate code for a processor running in big-endian mode; the default isto compile code for a little-endian processor. <br><dt><code>-mwords-little-endian</code> <dd>This option only applies when generating code for big-endian processors. Generate code for a little-endian word order but a big-endian byteorder. That is, a byte order of the form <code>32107654</code>. Note: thisoption should only be used if you require compatibility with code forbig-endian ARM processors generated by versions of the compiler prior to2.8. <br><dt><code>-malignment-traps</code> <dd>Generate code that will not trap if the MMU has alignment traps enabled. On ARM architectures prior to ARMv4, there were no instructions toaccess half-word objects stored in memory. However, when reading frommemory a feature of the ARM architecture allows a word load to be used,even if the address is unaligned, and the processor core will rotate thedata as it is being loaded. This option tells the compiler that suchmisaligned accesses will cause a MMU trap and that it should insteadsynthesize the access as a series of byte accesses. The compiler canstill use word accesses to load half-word data if it knows that theaddress is aligned to a word boundary. <p>This option is ignored when compiling for ARM architecture 4 or later,since these processors have instructions to directly access half-wordobjects in memory. <br><dt><code>-mno-alignment-traps</code> <dd>Generate code that assumes that the MMU will not trap unalignedaccesses. This produces better code when the target instruction setdoes not have half-word memory operations (i.e. implementations prior toARMv4). <p>Note that you cannot use this option to access unaligned word objects,since the processor will only fetch one 32-bit aligned object frommemory. <p>The default setting for most targets is <code>-mno-alignment-traps</code>, sincethis produces better code when there are no half-word memoryinstructions available. <br><dt><code>-mshort-load-bytes</code> <dd><dt><code>-mno-short-load-words</code> <dd>These are deprecated aliases for <code>-malignment-traps</code>.⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -