📄 usb_drv.lst
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500 3 break;
501 3 case 1:
502 3 stall_ep1 = 1;
503 3 break;
504 3 case 2:
505 3 stall_ep2 = 1;
506 3 break;
507 3 case 3:
508 3 stall_ep3 = 1;
509 3 break;
510 3 case 4:
511 3 stall_ep4 = 1;
512 3 break;
513 3 case 5:
514 3 stall_ep5 = 1;
515 3 break;
516 3 case 6:
517 3 stall_ep6 = 1;
518 3 break;
519 3 default:
520 3 //write_usb(EPC0,STALL);
521 3 break;
522 3 }
523 2 break;
524 2
525 2 default: /*UNDEFINED */
526 2 //write_usb(EPC0,STALL);
527 2 break;
528 2 }
529 1
530 1
531 1 }
532
533 void usb_get_status()
534 {
535 1 switch (usb_buf[0]&0x03) /*find request target */
536 1 {
537 2 case 0: /*DEVICE */
538 2 write_usb(TXD0,0); /*first byte is reserved */
539 2 break;
540 2
541 2 case 1: /*INTERFACE */
542 2 write_usb(TXD0,0); /*first byte is reserved */
543 2 break;
544 2
545 2 case 2: /*ENDPOINT */
546 2 switch (usb_buf[3]) /*find specific endpoint */
547 2 {
548 3 EPSTATUS(0);
549 3 EPSTATUS(1);
550 3 EPSTATUS(2);
551 3 EPSTATUS(3);
C51 COMPILER V7.06 USB_DRV 08/05/2007 09:42:58 PAGE 10
552 3 EPSTATUS(4);
553 3 EPSTATUS(5);
554 3 EPSTATUS(6);
555 3 default:
556 3 break;
557 3 }
558 2 break;
559 2
560 2 default: /*UNDEFINED */
561 2 //write_usb(EPC0,STALL);
562 2 break;
563 2 }
564 1 write_usb(TXD0,0); /*second byte is reserved */
565 1 }
566
567
568 void usb_mass_storage_reset()
569 {
570 1
571 1 }
572
573 void rx_1()
574 {
575 1
576 1 rxstat=read_usb(RXS1);
577 1 for(desc_idx=0; desc_idx<64; desc_idx++)
578 1 {
579 2 usb_buf[desc_idx] = read_usb(RXD1);
580 2 }
581 1
582 1 FLUSHRX1; /*make sure the RX is off */
583 1 FLUSHTX1; /*make sure the TX is off */
584 1 TI=1;//printf("\n%s\n",my_time);
585 1 printf("\n**********command*********\n");
586 1 for(desc_idx=0; desc_idx<64; desc_idx++)
587 1 {
588 2 if(desc_idx%8==0)printf("\n");
589 2
590 2 printf("%2.2X,", (uint)usb_buf[desc_idx]);
591 2
592 2 }
593 1 if(usb_buf[15]==0x12)
594 1 {
595 2 for(desc_idx=0,pbuffer=&(disk_descriptor.DeviceType);desc_idx<sizeof(disk_descriptor);desc_id
-x++)
596 2 {
597 3 write_usb(TXD1,*pbuffer++);
598 3 }
599 2
600 2
601 2 data_to_transfer=13;
602 2 usb_buf[0]=0x55;
603 2 usb_buf[1]=0x53;
604 2 usb_buf[2]=0x42;
605 2 usb_buf[3]=0x53;
606 2 usb_buf[12]=0x00;
607 2 dta_pid1=0; //enable the TX (DATA1)
608 2 TXEN1_PID;
609 2 }
610 1 else if(usb_buf[15]==0x23)
611 1 {
612 2 write_usb(TXD1,0x00);
C51 COMPILER V7.06 USB_DRV 08/05/2007 09:42:58 PAGE 11
613 2 write_usb(TXD1,0x00);
614 2 write_usb(TXD1,0x00);
615 2 write_usb(TXD1,0x10);
616 2 write_usb(TXD1,0x00);
617 2 write_usb(TXD1,0x10);
618 2 write_usb(TXD1,0x00);
619 2 write_usb(TXD1,0x00);
620 2 write_usb(TXD1,0x03);
621 2 write_usb(TXD1,0x00);
622 2 write_usb(TXD1,0x02);
623 2 write_usb(TXD1,0x00);
624 2 write_usb(TXD1,0x00);
625 2 write_usb(TXD1,0x10);
626 2 write_usb(TXD1,0x00);
627 2 write_usb(TXD1,0x00);
628 2 write_usb(TXD1,0x00);
629 2 write_usb(TXD1,0x00);
630 2 write_usb(TXD1,0x02);
631 2 write_usb(TXD1,0x00);
632 2
633 2 data_to_transfer=13;
634 2 usb_buf[0]=0x55;
635 2 usb_buf[1]=0x53;
636 2 usb_buf[2]=0x42;
637 2 usb_buf[3]=0x53;
638 2 usb_buf[8]=20;
639 2 usb_buf[12]=0x00;
640 2 dta_pid1=0; //enable the TX (DATA1)
641 2 TXEN1_PID;
642 2 }
643 1 else if(usb_buf[15]==0x25)
644 1 {
645 2 write_usb(TXD1,0x00);
646 2 write_usb(TXD1,0x0f);
647 2 write_usb(TXD1,0xff);
648 2 write_usb(TXD1,0xff);
649 2 write_usb(TXD1,0x00);
650 2 write_usb(TXD1,0x00);
651 2 write_usb(TXD1,0x02);
652 2 write_usb(TXD1,0x00);
653 2
654 2
655 2 data_to_transfer=13;
656 2 usb_buf[0]=0x55;
657 2 usb_buf[1]=0x53;
658 2 usb_buf[2]=0x42;
659 2 usb_buf[3]=0x53;
660 2 usb_buf[8]=8;
661 2 usb_buf[12]=0x00;
662 2 dta_pid1=0; //enable the TX (DATA1)
663 2 TXEN1_PID;
664 2 }
665 1 else if(usb_buf[15]==0x28)
666 1 {
667 2 // write_usb(TXD1,0x1);
668 2
669 2
670 2
671 2 data_to_transfer=0;
672 2 usb_buf[0]=0x55;
673 2 usb_buf[1]=0x53;
674 2 usb_buf[2]=0x42;
C51 COMPILER V7.06 USB_DRV 08/05/2007 09:42:58 PAGE 12
675 2 usb_buf[3]=0x53;
676 2 usb_buf[8]=1;
677 2 usb_buf[12]=0x01;
678 2 for(desc_idx=0;desc_idx<13;desc_idx++)
679 2 {
680 3 write_usb(TXD1,usb_buf[desc_idx]);
681 3 }
682 2 dta_pid1=0; //enable the TX (DATA1) /
683 2 TXEN1_PID;
684 2 }
685 1
686 1 }
687
688 void rx_2()
689 {
690 1 FLUSHRX2;
691 1 write_usb(RXC2, RX_EN);
692 1 dta_pid2=1; /*enable the TX (DATA1) */
693 1 TXEN2_PID;
694 1 }
695
696 void rx_3()
697 {
698 1 FLUSHRX3;
699 1 write_usb(RXC3, RX_EN);
700 1 dta_pid3=1; /*enable the TX (DATA1) */
701 1 TXEN3_PID;
702 1 }
703
704 void tx_0()
705 {
706 1
707 1 //write_usb(EPC0,NOSTALL);
708 1 txstat=read_usb(TXS0); /*get transmitter status */
709 1 /*if a transmission has completed successfully, check to see if */
710 1 /*we have anything else that needs to go out, otherwise turn the*/
711 1 /*receiver back on **********************************************/
712 1 if ((txstat & ACK_STAT) && (txstat & TX_DONE))
713 1 {
714 2 FLUSHTX0; /*flush TX0 and disable */
715 2 /*the desc. is sent in pieces; queue another piece if nec. */
716 2 if(data_to_transfer>0||zero_packet_flag==TRUE)
717 2 {
718 3 if(data_to_transfer==0) zero_packet_flag=FALSE;
719 3 send_desc_to_TXD0;
720 3 TXEN0_PID; /*enable TX, choose PID */
721 3 }
722 2 else
723 2 {
724 3 FLUSHRX0;
725 3 DelaymS(1);
726 3 write_usb(RXC0,RX_EN); /*re-enable the receiver */
727 3 }
728 2 }
729 1
730 1 /*otherwise something must have gone wrong with the previous ****/
731 1 /*transmission, or we got here somehow we shouldn't have ********/
732 1 else
733 1 {
734 2
735 2 }
736 1
C51 COMPILER V7.06 USB_DRV 08/05/2007 09:42:58 PAGE 13
737 1 /*we do this stuff for all tx_0 events **************************/
738 1 }
739
740 void tx_1()
741 {
742 1 txstat=read_usb(TXS1);
743 1 TI=1;printf("\n************");
744 1 FLUSHTX1; /*make sure the RX is off */
745 1 if(data_to_transfer>0)
746 1 {
747 2 for(desc_idx=0;desc_idx<data_to_transfer;desc_idx++)
748 2 {
749 3 write_usb(TXD1,usb_buf[desc_idx]);
750 3 }
751 2 data_to_transfer=0;
752 2
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