📄 usb_drv.c
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{
write_usb(EPC1,0); /*disable EP1 */
write_usb(EPC2,0); /*disable EP2 */
write_usb(EPC3,0); /*disable EP3 */
write_usb(EPC4,0); /*disable EP4 */
write_usb(EPC5,0); /*disable EP5 */
write_usb(EPC6,0); /*disable EP6 */
}
}
void usb_clear_feature()
{
switch(usb_buf[0]&0x03) /*find request target */
{
case 0: /*DEVICE */
//write_usb(EPC0,STALL);
break;
case 1: /*INTERFACE */
//write_usb(EPC0,STALL);
break;
case 2: /*ENDPOINT */
switch (usb_buf[3]&0x07) /*find specific endpoint */
{
case 0:
stall_ep0 = 0;
break;
case 1:
stall_ep1 = 0;
break;
case 2:
stall_ep2 = 0;
break;
case 3:
stall_ep3 = 0;
break;
case 4:
stall_ep4 = 0;
break;
case 5:
stall_ep5 = 0;
break;
case 6:
stall_ep6 = 0;
break;
default:
//write_usb(EPC0,STALL);
break;
}
break;
default: /*UNDEFINED */
//write_usb(EPC0,STALL);
break;
}
}
void usb_set_feature()
{
switch(usb_buf[0]&0x03) /*find request target */
{
case 0: /*DEVICE */
//write_usb(EPC0,STALL);
break;
case 1: /*INTERFACE */
//write_usb(EPC0,STALL);
break;
case 2: /*ENDPOINT */
switch (usb_buf[3]) /*find specific endpoint */
{
case 0:
stall_ep0 = 1;
break;
case 1:
stall_ep1 = 1;
break;
case 2:
stall_ep2 = 1;
break;
case 3:
stall_ep3 = 1;
break;
case 4:
stall_ep4 = 1;
break;
case 5:
stall_ep5 = 1;
break;
case 6:
stall_ep6 = 1;
break;
default:
//write_usb(EPC0,STALL);
break;
}
break;
default: /*UNDEFINED */
//write_usb(EPC0,STALL);
break;
}
}
void usb_get_status()
{
switch (usb_buf[0]&0x03) /*find request target */
{
case 0: /*DEVICE */
write_usb(TXD0,0); /*first byte is reserved */
break;
case 1: /*INTERFACE */
write_usb(TXD0,0); /*first byte is reserved */
break;
case 2: /*ENDPOINT */
switch (usb_buf[3]) /*find specific endpoint */
{
EPSTATUS(0);
EPSTATUS(1);
EPSTATUS(2);
EPSTATUS(3);
EPSTATUS(4);
EPSTATUS(5);
EPSTATUS(6);
default:
break;
}
break;
default: /*UNDEFINED */
//write_usb(EPC0,STALL);
break;
}
write_usb(TXD0,0); /*second byte is reserved */
}
void usb_mass_storage_reset()
{
}
void rx_1()
{
rxstat=read_usb(RXS1);
for(desc_idx=0; desc_idx<64; desc_idx++)
{
usb_buf[desc_idx] = read_usb(RXD1);
}
FLUSHRX1; /*make sure the RX is off */
FLUSHTX1; /*make sure the TX is off */
TI=1;//printf("\n%s\n",my_time);
printf("\n**********command*********\n");
for(desc_idx=0; desc_idx<64; desc_idx++)
{
if(desc_idx%8==0)printf("\n");
printf("%2.2X,", (uint)usb_buf[desc_idx]);
}
if(usb_buf[15]==0x12)
{
for(desc_idx=0,pbuffer=&(disk_descriptor.DeviceType);desc_idx<sizeof(disk_descriptor);desc_idx++)
{
write_usb(TXD1,*pbuffer++);
}
data_to_transfer=13;
usb_buf[0]=0x55;
usb_buf[1]=0x53;
usb_buf[2]=0x42;
usb_buf[3]=0x53;
usb_buf[12]=0x00;
dta_pid1=0; //enable the TX (DATA1)
TXEN1_PID;
}
else if(usb_buf[15]==0x23)
{
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x10);
write_usb(TXD1,0x00);
write_usb(TXD1,0x10);
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x03);
write_usb(TXD1,0x00);
write_usb(TXD1,0x02);
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x10);
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x02);
write_usb(TXD1,0x00);
data_to_transfer=13;
usb_buf[0]=0x55;
usb_buf[1]=0x53;
usb_buf[2]=0x42;
usb_buf[3]=0x53;
usb_buf[8]=20;
usb_buf[12]=0x00;
dta_pid1=0; //enable the TX (DATA1)
TXEN1_PID;
}
else if(usb_buf[15]==0x25)
{
write_usb(TXD1,0x00);
write_usb(TXD1,0x0f);
write_usb(TXD1,0xff);
write_usb(TXD1,0xff);
write_usb(TXD1,0x00);
write_usb(TXD1,0x00);
write_usb(TXD1,0x02);
write_usb(TXD1,0x00);
data_to_transfer=13;
usb_buf[0]=0x55;
usb_buf[1]=0x53;
usb_buf[2]=0x42;
usb_buf[3]=0x53;
usb_buf[8]=8;
usb_buf[12]=0x00;
dta_pid1=0; //enable the TX (DATA1)
TXEN1_PID;
}
else if(usb_buf[15]==0x28)
{
// write_usb(TXD1,0x1);
data_to_transfer=0;
usb_buf[0]=0x55;
usb_buf[1]=0x53;
usb_buf[2]=0x42;
usb_buf[3]=0x53;
usb_buf[8]=1;
usb_buf[12]=0x01;
for(desc_idx=0;desc_idx<13;desc_idx++)
{
write_usb(TXD1,usb_buf[desc_idx]);
}
dta_pid1=0; //enable the TX (DATA1) /
TXEN1_PID;
}
}
void rx_2()
{
FLUSHRX2;
write_usb(RXC2, RX_EN);
dta_pid2=1; /*enable the TX (DATA1) */
TXEN2_PID;
}
void rx_3()
{
FLUSHRX3;
write_usb(RXC3, RX_EN);
dta_pid3=1; /*enable the TX (DATA1) */
TXEN3_PID;
}
void tx_0()
{
//write_usb(EPC0,NOSTALL);
txstat=read_usb(TXS0); /*get transmitter status */
/*if a transmission has completed successfully, check to see if */
/*we have anything else that needs to go out, otherwise turn the*/
/*receiver back on **********************************************/
if ((txstat & ACK_STAT) && (txstat & TX_DONE))
{
FLUSHTX0; /*flush TX0 and disable */
/*the desc. is sent in pieces; queue another piece if nec. */
if(data_to_transfer>0||zero_packet_flag==TRUE)
{
if(data_to_transfer==0) zero_packet_flag=FALSE;
send_desc_to_TXD0;
TXEN0_PID; /*enable TX, choose PID */
}
else
{
FLUSHRX0;
DelaymS(1);
write_usb(RXC0,RX_EN); /*re-enable the receiver */
}
}
/*otherwise something must have gone wrong with the previous ****/
/*transmission, or we got here somehow we shouldn't have ********/
else
{
}
/*we do this stuff for all tx_0 events **************************/
}
void tx_1()
{
txstat=read_usb(TXS1);
TI=1;printf("\n************");
FLUSHTX1; /*make sure the RX is off */
if(data_to_transfer>0)
{
for(desc_idx=0;desc_idx<data_to_transfer;desc_idx++)
{
write_usb(TXD1,usb_buf[desc_idx]);
}
data_to_transfer=0;
TXEN1_PID;
}
else
{
write_usb(RXC1,RX_EN);
}
}
void tx_2()
{}
void tx_3()
{}
void usb_alt()
{
evnt = read_usb(ALTEV); /*check the events */
if(evnt & RESET_A) /*reset event */
{
write_usb(NFSR,RST_ST); /*enter reset state */
write_usb(FAR,AD_EN+0); /*set default address */
write_usb(EPC0,0x00); /*enable EP0 only */
FLUSHTX0; /*flush TX0 and disable */
write_usb(RXC0,RX_EN); /*enable the receiver */
write_usb(ALTMSK,SD3+RESET_A);
write_usb(NFSR,OPR_ST); /*go operational */
}
else if(evnt & (SD3 | SD5) ) /*suspend event */
{
write_usb(ALTMSK,RESUME_A + RESET_A); /*adjust interrupts */
write_usb(NFSR,SUS_ST); /*enter suspend state */
}
else if(evnt & RESUME_A) /*resume event */
{
write_usb(ALTMSK,SD3+RESET_A); /*adjust interrupts */
write_usb(NFSR,OPR_ST); /*go operational */
// write_usb(RXC0,RX_EN);
}
else /*spurious alt. event! */
{
}
}
void nak0()
{
/*important note: even after servicing a NAK, another NAK */
/*interrupt may occur if another 'OUT' or 'IN' packet comes in */
/*during our NAK service. */
/*if we're currently doing something that requires multiple 'IN'*/
/*transactions, 'OUT' requests will get NAKs because the FIFO is*/
/*busy with the TX data. Since the 'OUT' here means a premature*/
/*end to the previous transfer, just flush the FIFO, disable the*/
/*transmitter, and re-enable the receiver. */
if (data_to_transfer>0||zero_packet_flag==TRUE) /*get_descr status stage? */
{
data_to_transfer=0; /*exit get_descr mode */
zero_packet_flag=FALSE;
}
FLUSHTX0; /*flush TX0 and disable */
FLUSHRX0;
DelaymS(1);
write_usb(RXC0,RX_EN); /*re-enable the receiver */
/*we do this stuff for all nak0 events **************************/
}
void nakO1()
{
//printf("\nOUT");write_usb(RXC1,RX_EN);
}
void nakI1()
{
}
void nak2()
{
}
void nak3()
{
}
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