cpu.v

this contains the impementation of 5 stage superscalar piepline in verilog

  
  // =========================================================================
  // Stage 2 - Decode Stage
  // -------------------------------------------------------------------------
  
  
  
  
  
  
  if(IFIDIR!=NOP) begin 
        
     
                              if(IFIDop==ALUop)begin
                                             if((SRegs[IFIDIR[25:21]]!=1) && (SRegs[IFIDIR[20:16]]!=1))begin //rs and rt not equal to rd
                                                 SRegs[IFIDIR[15:11]]<=1; //set rd 
                                                 IDEXA <= Regs[IFIDIR[25:21]]; 
                                                IDEXB <= Regs[IFIDIR[20:16]]; 
                                                IDEXIR <= IFIDIR;  
                                                if(IFIDIR2!=NOP) begin
                                                      if(IFIDop2==ALUop)begin   //I2 an ALU op
                                                                  if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
                                                                    SRegs[IFIDIR2[15:11]] <=1; //set rd
                                                                    IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2<=IFIDIR2;
                                                                            if(IFIDIR[15:11]==IFIDIR[15:11]) begin//WAW check 
                                                                                IDEXIR<=IFIDIR;
                                                                                WAWFlag<=1;
                                                                            end   
                                                                 end else begin
                                                                   IDEXIR2<= NOP;
                                                                   HFlag2<=3;
                                                                 end 
                                                           
                                                      end else if(IFIDop2==BEQ || IFIDop2==BNE)begin
                                                                  if((SRegs[IFIDIR2[25:21]]!=1 )&& (SRegs[IFIDIR2[20:16]]!=1))begin
                                                                    BFlag2<=3; //introduce 3 NOPs
                                                                    IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2<= IFIDIR2;       
                                                                end else begin
                                                                   IDEXIR2<= NOP;
                                                                   HFlag2<=3;
                                                                 end
                                                    end else if(IFIDop2==LW) begin
                                                                 SRegs[IFIDIR2[20:16]]<=1;     //set dest to 1
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;  
                                                                     if(IFIDIR[20:15]==IFIDIR2[15:11]) begin//WAW ALU-LW check
                                                                              IFIDIR<=NOP;
                                                                              WAWFlag<=1;
                                                                    end
                                                    end  else begin
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;
                                                    end
                                         end   else begin  //I2 is a NOP
                                                        IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                        IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                        IDEXIR2 <= IFIDIR2; 
                                                     end          
                                 end else begin //I1 fails RAW test
                                              IDEXIR<=NOP;
                                              IDEXIR2<=NOP;
                                              HFlag<=3;
                                        end      
                                                        
                                                    
                            end else if(IFIDop==BNE ||IFIDop ==BEQ) begin 
                                                     if((SRegs[IFIDIR[25:21]]!=1) && (SRegs[IFIDIR[20:16]]!=1))begin                           
                                                            BFlag<=3;   //introduce 3 more NOPs ..implies 1st instruction a branch
                                                            IDEXA2 <= Regs[IFIDIR[25:21]]; 
                                                            IDEXB2 <= Regs[IFIDIR[20:16]]; // get registers
                                                            IDEXIR2<=IFIDIR; //pass along IR--can happen anywhere, since this affects next stage only!
                                                            IDEXIR <= NOP;
                                                            SwapFlag<=1; //swap instructions and send 1st to ALU 2
                                                     end else begin 
                                                             HFlag<=3;
                                                             IDEXIR<=NOP;
                                                             IDEXIR2<=NOP;
                                                      end
                            end else if(IFIDop==LW)begin
                                                      SRegs[IFIDIR[20:16]]<=1;     //set dest to 1
                                                      IDEXA <= Regs[IFIDIR[25:21]]; 
                                                      IDEXB <= Regs[IFIDIR[20:16]]; 
                                                      IDEXIR <=IFIDIR;
                                          if(IFIDIR2!=NOP) begin              
                                                      if(IFIDop2==ALUop)begin   //I2 an ALU op
                                                                  if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
                                                                    SRegs[IFIDIR2[15:11]] <=1; //set rd
                                                                    IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;
                                                                          //WAW  LW-->ALUop 
                                                                             if(IFIDIR[20:16]==IFIDIR2[15:11])begin
                                                                               IDEXIR<=IFIDIR;
                                                                               WAWFlag<=1;
                                                                             end
                                                                 end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end 
                                                           
                                                      end else if(IFIDop2==BEQ || IFIDop2==BNE)begin
                                                                  if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
                                                                    BFlag2<=3; //introduce 3 NOPs
                                                                    IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;       
                                                                end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end
                                                    end else if(IFIDop2==LW) begin
                                                                 SRegs[IFIDIR2[20:16]]<=1;     //set dest to 1
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;  
                                                                     if(IFIDIR[15:11]==IFIDIR2[15:11])begin //LW-LW war check
                                                                       IFIDIR<=NOP;
                                                                       WAWFlag<=1;
                                                                    end
                                                    end  else begin
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <=IFIDIR2;
                                                    end  
                                       end else begin //I2 is a NOP
                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                 IDEXIR2 <= IFIDIR2;
                                                 end
                                                 
                                                 
                        end  else if(IFIDop==SW)begin
                                             if(SRegs[IFIDIR[20:16]]!=1) begin
                                                         IDEXA <= Regs[IFIDIR[25:21]]; 
                                                         IDEXB <= Regs[IFIDIR[20:16]]; 
                                                         IDEXIR <= IFIDIR;
                                                      if(IFIDIR2!=NOP) begin   
                                                          if(IFIDop2==ALUop)begin   //I2 an ALU op
                                                                  if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
                                                                    SRegs[IFIDIR2[15:11]] <=1; //set rd
                                                                    IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;
                                                                 end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end 
                                                           
                                                           end else if(IFIDop2==BEQ || IFIDop2==BNE)begin
                                                                  if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
                                                                    BFlag2<=3; //introduce 3 NOPs
                                                                    IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;       
                                                                end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end
                                                          end else if(IFIDop2==LW) begin
                                                                 SRegs[IFIDIR2[20:16]]<=1;     //set dest to 1
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;  
                                                          end  else begin
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;
                                                          end 
                                                    end else begin //I2 is a NOP
                                                               IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;