cpu_part1.v

this contains the impementation of 5 stage superscalar piepline in verilog

	                                                    end
	                          end else if(IFIDop==LW)begin
	                                                    SRegs[IFIDIR[20:16]]<=1;     //set dest to 1
                                                      IDEXA <= Regs[IFIDIR[25:21]]; 
                                                      IDEXB <= Regs[IFIDIR[20:16]]; 
                                                      IDEXIR <=IFIDIR;
                                          if(IFIDIR2!=NOP) begin              
                                                      if(IFIDop2==ALUop)begin   //I2 an ALU op
	    	                                                          if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
	    	                                                            SRegs[IFIDIR2[15:11]] <=1; //set rd
	    	                                                            IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;
                                                                          //WAW  LW-->ALUop 
                                                                             if(IFIDIR[20:16]==IFIDIR2[15:11])
                                                                               IDEXIR<=NOP;
                                                                 end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end 
                                                           
	    	                                              end else if(IFIDop2==BEQ || IFIDop2==BNE)begin
	    	                                                          if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
	    	                                                            BFlag2<=3; //introduce 3 NOPs
	    	                                                            IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;       
                                                                end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end
                                                    end else if(IFIDop2==LW) begin
                                                                 SRegs[IFIDIR2[20:16]]<=1;     //set dest to 1
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;  
                                                                     if(IFIDIR[15:11]==IFIDIR2[15:11]) //LW-LW war check
                                                                       IFIDIR<=NOP;
                                                    end  else begin
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <=IFIDIR2;
                                                    end  
                                       end else begin //I2 is a NOP
                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                 IDEXIR2 <= IFIDIR2;
                                                 end
                                                 
                                                 
                        end  else if(IFIDop==SW)begin
                                             if(SRegs[IFIDIR[20:16]]!=1) begin
                                                         IDEXA <= Regs[IFIDIR[25:21]]; 
                                                         IDEXB <= Regs[IFIDIR[20:16]]; 
                                                         IDEXIR <= IFIDIR;
                                                      if(IFIDIR2!=NOP) begin   
                                                          if(IFIDop2==ALUop)begin   //I2 an ALU op
	    	                                                          if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
	    	                                                            SRegs[IFIDIR2[15:11]] <=1; //set rd
	    	                                                            IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;
                                                                 end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end 
                                                           
	    	                                                   end else if(IFIDop2==BEQ || IFIDop2==BNE)begin
	    	                                                          if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
	    	                                                            BFlag2<=3; //introduce 3 NOPs
	    	                                                            IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;       
                                                                end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end
                                                          end else if(IFIDop2==LW) begin
                                                                 SRegs[IFIDIR2[20:16]]<=1;     //set dest to 1
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;  
                                                          end  else begin
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;
                                                          end 
                                                    end else begin //I2 is a NOP
                                                               IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;
                                                              end 
                                             end else begin //I1 fails RAW test
                                                              HFlag<=3;
                                                              IDEXIR<=NOP;
                                                              IDEXIR2<=NOP;
                                                end              
                                                         
                          end //End of check for RAW hazards                                                                
	                      
	end else begin 
	                 //I1 is a NOP    
                IDEXA <= Regs[IFIDIR[25:21]]; 
                IDEXB <= Regs[IFIDIR[20:16]]; 
                IDEXIR <= IFIDIR; 
	                          if(IFIDIR2!=NOP) begin
	    	                                              if(IFIDop2==ALUop)begin   //I2 an ALU op
	    	                                                          if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
	    	                                                            SRegs[IFIDIR2[15:11]] <=1; //set rd
	    	                                                            IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;
                                                                            
                                                                 end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end 
                                                           
	    	                                              end else if(IFIDop2==BEQ || IFIDop2==BNE)begin
	    	                                                          if((SRegs[IFIDIR2[25:21]]!=1) && (SRegs[IFIDIR2[20:16]]!=1))begin
	    	                                                            BFlag2<=3; //introduce 3 NOPs
	    	                                                            IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                   IDEXIR2 <= IFIDIR2;       
                                                                end else begin
                                                                   IDEXIR2 <= NOP;
                                                                   HFlag2<=3;
                                                                 end
                                                    end else if(IFIDop2==LW) begin
                                                                 SRegs[IFIDIR2[20:16]]<=1;     //set dest to 1
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;  
                                                    end  else begin
                                                                 IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                                                 IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                                                 IDEXIR2 <= IFIDIR2;
                                                    end
                           end   else begin  //I2 is a NOP
                                   IDEXA2 <= Regs[IFIDIR2[25:21]]; 
                                   IDEXB2 <= Regs[IFIDIR2[20:16]]; 
                                   IDEXIR2 <= IFIDIR2; 
                                   end     
      end                                                  
	  
	            
     
     
	// =========================================================================
	// Stage 3 - Execution Stage
	// -------------------------------------------------------------------------

	   if ((IDEXop==LW) ||(IDEXop==SW)) // address calculation
		   EXMEMALUOut <= IDEXA +{{16{IDEXIR[15]}}, IDEXIR[15:0]};
		     
	   else if (IDEXop==ALUop) 
		   case (IDEXIR[5:0]) //case for the various R-type instructions
			   6'h20: EXMEMALUOut <= Ain + Bin; //add operation
			   6'h01: EXMEMALUOut <= Ain - Bin; //sub operation
			   6'h25: EXMEMALUOut <= Ain | Bin; //OR operation
			   6'h24: EXMEMALUOut <= Ain & Bin; //AND operation
			   //6'h27: EXMEMALUOut <= Ain ~| Bin; //NOR operation
			   default: ; //other R-type operations: subtract, SLT, etc.
		   endcase
		   		     
	   EXMEMIR <= IDEXIR; EXMEMB <= IDEXB; //pass along the IR & B register
	   
	   if ((IDEXop2==LW) ||(IDEXop2==SW)) // address calculation
		   EXMEMALUOut2 <= IDEXA2 +{{16{IDEXIR2[15]}}, IDEXIR2[15:0]};
	   else if (IDEXop2==ALUop) 
		   case (IDEXIR2[5:0]) //case for the various R-type instructions
			   6'h20: EXMEMALUOut <= Ain2 + Bin2; //add operation
			   6'h01: EXMEMALUOut <= Ain2 - Bin2; //sub operation
			   6'h25: EXMEMALUOut <= Ain2 | Bin2; //OR operation
			   6'h24: EXMEMALUOut <= Ain2 & Bin2; //AND operation
			   //6'h27: EXMEMALUOut <= Ain2 nor Bin2; //NOR operation
			   default: ; //other R-type operations: subtract, SLT, etc.
		   endcase
		   else if(IDEXop2==BEQ)begin
		                if(IDEXIR2[25:21]==IDEXIR2[20:16]) begin
		                   if(SwapFlag==1)begin
		                      SwapFlag<=0;
		                      BTFlag<=1;
		                   end   
		                   else 
		                      BTFlag2<=1;
		                end   else SwapFlag<=0;
		        end
		   else if(IDEXop2==BNE)begin
		                if(IDEXIR2[25:21]!=IDEXIR2[20:16])begin
		                      if(SwapFlag==1) begin
		                            BTFlag<=1;
		                            SwapFlag<=0;
		                      end      
		                      else
		                            BTFlag2<=1;
		                end    else SwapFlag<=0;        
		        end  
	  
	   EXMEMIR2 <= IDEXIR2; EXMEMB2 <= IDEXB2; //pass along the IR & B register
	
	// =========================================================================
	// Stage 4 - Memory Stage
	// -------------------------------------------------------------------------

	   if (EXMEMop==ALUop) begin
		   MEMWBValue <= EXMEMALUOut; //pass along ALU result
		   SRegs[EXMEMIR[15:11]]<=0;
		   end
	   else if (EXMEMop == LW) begin
		   MEMWBValue <= DMemory[EXMEMALUOut>>2];
		   SRegs[EXMEMIR[20:16]]<=0;
		   end
	   else if (EXMEMop == SW) 
		   DMemory[EXMEMALUOut>>2] <=EXMEMB; //store
	  
	   MEMWBIR <= EXMEMIR; //pass along IR
	   
	   if (EXMEMop2==ALUop) begin
	     SRegs[EXMEMIR2[15:11]]<=0;
		   MEMWBValue2 <= EXMEMALUOut2; //pass along ALU result
		   end
	   else if (EXMEMop2 == LW) begin
		   MEMWBValue2 <= DMemory[EXMEMALUOut2>>2];
		   SRegs[EXMEMIR2[20:16]]<=0;
		  end 
	   else if (EXMEMop2 == SW) 
		   DMemory[EXMEMALUOut2>>2]<=EXMEMB2; //store
	   
	   MEMWBIR2 <= EXMEMIR2; //pass along IR

	// =========================================================================
	// Stage 5 - Write Back stage
	// -------------------------------------------------------------------------

	   if ((MEMWBop==ALUop) && (MEMWBrd != 0)) // update registers if ALU operation and destination not 0
		   Regs[MEMWBrd] <= MEMWBValue; // ALU operation
	   else if ((MEMWBop == LW)&& (MEMWBrt != 0)) // Update registers if load and destination not 0
		   Regs[MEMWBrt] <= MEMWBValue;
	   
	   if ((MEMWBop2==ALUop) && (MEMWBrd2 != 0)) // update registers if ALU operation and destination not 0
		   Regs[MEMWBrd2] <= MEMWBValue2; // ALU operation
	   else if ((MEMWBop2 == LW)&& (MEMWBrt2 != 0)) // Update registers if load and destination not 0
		   Regs[MEMWBrt2] <= MEMWBValue2;
	   
	   
	   end // end always
	   
	
		
	
endmodule