runcpu.v

this contains the impementation of 5 stage superscalar piepline in verilog

module runCPU;
	reg CLK;

	CPU mySuperScaler(CLK);

	initial
	begin

	#1 CLK = 0;

	#200 $stop;
	end

	always
	begin
	#10 CLK = ~CLK;
	end

endmodule