dsp28_gpio.c

AD7888的调试程序,串行模式

//
//      TMDX ALPHA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:	DSP28_Gpio.c
//
// TITLE:	DSP28 General Purpose I/O Initialization & Support Functions.
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
//  0.56| 20 May 2002 | L.H. | No change
//  0.57| 27 May 2002 | L.H. | No change
//###########################################################################

#include "DSP28_Device.h"

	
//---------------------------------------------------------------------------
// InitGpio: 
//---------------------------------------------------------------------------
// This function initializes the Gpio to a known state.
//
void InitGpio(void)
{

// Set GPIO F port pins,bit0 as ouput,bit1 as input,bit2 as output, bit3 as ouput
// Input Qualifier =0, none
     EALLOW;

     //GpioMuxRegs.GPAMUX.all=0x073f;//0000 0111 0011 1111
     GpioMuxRegs.GPAMUX.bit.C3TRIP_GPIOA15=0;
     GpioMuxRegs.GPAMUX.bit.C2TRIP_GPIOA14=0;
     GpioMuxRegs.GPAMUX.bit.C1TRIP_GPIOA13=0;
     GpioMuxRegs.GPAMUX.bit.TCLKINA_GPIOA12=0;
     GpioMuxRegs.GPAMUX.bit.TDIRA_GPIOA11=0;
     GpioMuxRegs.GPAMUX.bit.CAP3QI1_GPIOA10=1;
     GpioMuxRegs.GPAMUX.bit.CAP2Q2_GPIOA9=1;
     GpioMuxRegs.GPAMUX.bit.CAP1Q1_GPIOA8=1;
     GpioMuxRegs.GPAMUX.bit.T2PWM_GPIOA7=0;
     GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6=0;
     GpioMuxRegs.GPAMUX.bit.PWM6_GPIOA5=1;
     GpioMuxRegs.GPAMUX.bit.PWM5_GPIOA4=1;
     GpioMuxRegs.GPAMUX.bit.PWM4_GPIOA3=1;
     GpioMuxRegs.GPAMUX.bit.PWM3_GPIOA2=1;
     GpioMuxRegs.GPAMUX.bit.PWM2_GPIOA1=1;
     GpioMuxRegs.GPAMUX.bit.PWM1_GPIOA0=1;
     
     
     GpioMuxRegs.GPADIR.bit.GPIOA6=0; //input
     GpioMuxRegs.GPADIR.bit.GPIOA7=0; //input
     GpioMuxRegs.GPADIR.bit.GPIOA11=0; //input
     GpioMuxRegs.GPADIR.bit.GPIOA12=0; //inaput
     GpioMuxRegs.GPADIR.bit.GPIOA13=1; //output
     GpioMuxRegs.GPADIR.bit.GPIOA14=0; //input
     GpioMuxRegs.GPADIR.bit.GPIOA15=1; //output
     GpioDataRegs.GPADAT.all=0x0000;
     
     GpioMuxRegs.GPBMUX.all=0x073f; //0000,0111,0011,1111
     GpioMuxRegs.GPBDIR.all=0xf880; //1111,1000,1000,0000  
     GpioDataRegs.GPBDAT.all=0x0000; 
     
     GpioMuxRegs.GPDMUX.bit.T1CTRIP_PDPA_GPIOD0=0;
     GpioMuxRegs.GPDMUX.bit.T2CTRIP_SOCA_GPIOD1=0;
     GpioMuxRegs.GPDMUX.bit.T3CTRIP_PDPB_GPIOD5=0;
     GpioMuxRegs.GPDMUX.bit.T4CTRIP_SOCB_GPIOD6=0;
     GpioMuxRegs.GPDDIR.bit.GPIOD0=1;  //output
     GpioMuxRegs.GPDDIR.bit.GPIOD1=1;  //
     GpioMuxRegs.GPDDIR.bit.GPIOD5=0;
     GpioMuxRegs.GPDDIR.bit.GPIOD6=0;

     
     GpioMuxRegs.GPEMUX.bit.XINT1_XBIO_GPIOE0=0;
     GpioMuxRegs.GPEMUX.bit.XINT2_ADCSOC_GPIOE1=0;
     GpioMuxRegs.GPEMUX.bit.XNMI_XINT13_GPIOE2=0;
     GpioMuxRegs.GPEDIR.bit.GPIOE0=0;
     GpioMuxRegs.GPEDIR.bit.GPIOE1=0;
     GpioMuxRegs.GPEDIR.bit.GPIOE2=1;
     GpioDataRegs.GPEDAT.bit.GPIOE0=0;
     GpioDataRegs.GPEDAT.bit.GPIOE1=0;
     GpioDataRegs.GPEDAT.bit.GPIOE2=0;
     
  	 GpioMuxRegs.GPFMUX.bit.SPISIMOA_GPIOF0 = 0;
  	 GpioMuxRegs.GPFMUX.bit.SPISOMIA_GPIOF1 = 0;
  	 GpioMuxRegs.GPFMUX.bit.SPICLKA_GPIOF2  = 0;
  	 GpioMuxRegs.GPFMUX.bit.SPISTEA_GPIOF3 = 0;
  	 GpioMuxRegs.GPFDIR.bit.GPIOF0 = 0;
  	 GpioMuxRegs.GPFDIR.bit.GPIOF1 = 1;
  	 GpioMuxRegs.GPFDIR.bit.GPIOF2 = 1;
  	 GpioMuxRegs.GPFDIR.bit.GPIOF3 = 1;
     EDIS;

}	
	
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// No more.
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