dq01.map.qmsg

1

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus60/libraries/others/maxplus2/7408.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/7408.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7408 " "Info: Found entity 1: 7408" {  } { { "7408.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7408.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7408 7408:inst1 " "Info: Elaborating entity \"7408\" for hierarchy \"7408:inst1\"" {  } { { "dq01.bdf" "inst1" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 784 392 456 824 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7408:inst1 " "Info: Elaborated megafunction instantiation \"7408:inst1\"" {  } { { "dq01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 784 392 456 824 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus60/libraries/others/maxplus2/74190.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/74190.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74190 " "Info: Found entity 1: 74190" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74190 74190:inst6 " "Info: Elaborating entity \"74190\" for hierarchy \"74190:inst6\"" {  } { { "dq01.bdf" "inst6" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 784 816 936 944 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74190:inst6 " "Info: Elaborated megafunction instantiation \"74190:inst6\"" {  } { { "dq01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 784 816 936 944 "inst6" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus60/libraries/others/maxplus2/7402.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/7402.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7402 " "Info: Found entity 1: 7402" {  } { { "7402.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7402.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7402 7402:inst30 " "Info: Elaborating entity \"7402\" for hierarchy \"7402:inst30\"" {  } { { "dq01.bdf" "inst30" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 624 704 768 664 "inst30" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7402:inst30 " "Info: Elaborated megafunction instantiation \"7402:inst30\"" {  } { { "dq01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 624 704 768 664 "inst30" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus60/libraries/others/maxplus2/7447.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/7447.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7447 " "Info: Found entity 1: 7447" {  } { { "7447.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7447.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7447 7447:inst " "Info: Elaborating entity \"7447\" for hierarchy \"7447:inst\"" {  } { { "dq01.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 592 1056 1176 752 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7447:inst " "Info: Elaborated megafunction instantiation \"7447:inst\"" {  } { { "dq01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/交通灯 完整版ver2/交通灯 完整版/dq01.bdf" { { 592 1056 1176 752 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "22 " "Info: Ignored 22 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "22 " "Info: Ignored 22 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74160:inst7\|9 data_in GND " "Warning: Reduced register \"74160:inst7\|9\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74160:inst7\|8 data_in GND " "Warning: Reduced register \"74160:inst7\|8\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." { { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|49 74190:inst21\|49~\$emulated 74190:inst21\|49~35 " "Info: Register \"74190:inst21\|49\" converted into equivalent circuit using register \"74190:inst21\|49~\$emulated\" and latch \"74190:inst21\|49~35\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|50 74190:inst21\|50~\$emulated 74190:inst21\|50~37 " "Info: Register \"74190:inst21\|50\" converted into equivalent circuit using register \"74190:inst21\|50~\$emulated\" and latch \"74190:inst21\|50~37\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|48 74190:inst21\|48~\$emulated 74190:inst21\|48~8 " "Info: Register \"74190:inst21\|48\" converted into equivalent circuit using register \"74190:inst21\|48~\$emulated\" and latch \"74190:inst21\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst24\|48 74190:inst24\|48~\$emulated 74190:inst24\|48~8 " "Info: Register \"74190:inst24\|48\" converted into equivalent circuit using register \"74190:inst24\|48~\$emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst24\|50 74190:inst24\|50~\$emulated 74190:inst24\|48~8 " "Info: Register \"74190:inst24\|50\" converted into equivalent circuit using register \"74190:inst24\|50~\$emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|49 74190:inst33\|49~\$emulated 74190:inst24\|48~8 " "Info: Register \"74190:inst33\|49\" converted into equivalent circuit using register \"74190:inst33\|49~\$emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|50 74190:inst33\|50~\$emulated 74190:inst24\|48~8 " "Info: Register \"74190:inst33\|50\" converted into equivalent circuit using register \"74190:inst33\|50~\$emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|48 74190:inst33\|48~\$emulated 74190:inst24\|48~8 " "Info: Register \"74190:inst33\|48\" converted into equivalent circuit using register \"74190:inst33\|48~\$emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst35\|50 74190:inst35\|50~\$emulated 74190:inst35\|50~37 " "Info: Register \"74190:inst35\|50\" converted into equivalent circuit using register \"74190:inst35\|50~\$emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst35\|48 74190:inst35\|48~\$emulated 74190:inst35\|50~37 " "Info: Register \"74190:inst35\|48\" converted into equivalent circuit using register \"74190:inst35\|48~\$emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|48 74190:inst5\|48~\$emulated 74190:inst35\|50~37 " "Info: Register \"74190:inst5\|48\" converted into equivalent circuit using register \"74190:inst5\|48~\$emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|49 74190:inst5\|49~\$emulated 74190:inst35\|50~37 " "Info: Register \"74190:inst5\|49\" converted into equivalent circuit using register \"74190:inst5\|49~\$emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|50 74190:inst5\|50~\$emulated 74190:inst35\|50~37 " "Info: Register \"74190:inst5\|50\" converted into equivalent circuit using register \"74190:inst5\|50~\$emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst6\|48 74190:inst6\|48~\$emulated 74190:inst6\|48~8 " "Info: Register \"74190:inst6\|48\" converted into equivalent circuit using register \"74190:inst6\|48~\$emulated\" and latch \"74190:inst6\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst6\|50 74190:inst6\|50~\$emulated 74190:inst6\|48~8 " "Info: Register \"74190:inst6\|50\" converted into equivalent circuit using register \"74190:inst6\|50~\$emulated\" and latch \"74190:inst6\|48~8\"" {  } { { "74190.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0}  } {  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "207 " "Info: Implemented 207 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "34 " "Info: Implemented 34 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "170 " "Info: Implemented 170 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 18 15:42:39 2007 " "Info: Processing ended: Tue Dec 18 15:42:39 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}