dq01.map.rpt

1

+---------------------------------------------+--------------+
; Resource                                    ; Usage        ;
+---------------------------------------------+--------------+
; Estimated Total logic elements              ; 168          ;
; Total combinational functions               ; 168          ;
; Logic element usage by number of LUT inputs ;              ;
;     -- 4 input functions                    ; 95           ;
;     -- 3 input functions                    ; 50           ;
;     -- <=2 input functions                  ; 23           ;
;         -- Combinational cells for routing  ; 0            ;
; Logic elements by mode                      ;              ;
;     -- normal mode                          ; 168          ;
;     -- arithmetic mode                      ; 0            ;
; Total registers                             ; 53           ;
; I/O pins                                    ; 37           ;
; Maximum fan-out node                        ; 7408:inst3|4 ;
; Maximum fan-out                             ; 52           ;
; Total fan-out                               ; 744          ;
; Average fan-out                             ; 2.88         ;
+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |dq01                      ; 168 (9)           ; 53 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 37   ; 0            ; |dq01               ;
;    |7408:inst1|            ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|7408:inst1    ;
;    |7408:inst3|            ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|7408:inst3    ;
;    |74160:inst7|           ; 2 (2)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74160:inst7   ;
;    |74175:inst45|          ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74175:inst45  ;
;    |74190:inst21|          ; 12 (12)           ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74190:inst21  ;
;    |74190:inst24|          ; 9 (9)             ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74190:inst24  ;
;    |74190:inst33|          ; 9 (9)             ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74190:inst33  ;
;    |74190:inst35|          ; 9 (9)             ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74190:inst35  ;
;    |74190:inst5|           ; 10 (10)           ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74190:inst5   ;
;    |74190:inst6|           ; 10 (10)           ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74190:inst6   ;
;    |74292:inst27|          ; 33 (33)           ; 25 (25)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|74292:inst27  ;
;    |7447:inst26|           ; 15 (15)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|7447:inst26   ;
;    |7447:inst39|           ; 16 (16)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|7447:inst39   ;
;    |7447:inst40|           ; 16 (16)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|7447:inst40   ;
;    |7447:inst|             ; 16 (16)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |dq01|7447:inst     ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 53    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 24    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Tue Dec 18 15:42:31 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dq01 -c dq01
Info: Found 1 design units, including 1 entities, in source file dq01.bdf
    Info: Found entity 1: dq01
Info: Elaborating entity "dq01" for the top level hierarchy
Warning: Port "3D" of type 74175 and instance "inst45" is missing source signal
Warning: Port "CLRN" of type 74160 and instance "inst7" is missing source signal
Warning: Port "4D" of type 74175 and instance "inst45" is missing source signal
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/7404.bdf
    Info: Found entity 1: 7404
Info: Elaborating entity "7404" for hierarchy "7404:inst22"
Info: Elaborated megafunction instantiation "7404:inst22"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/74175.bdf
    Info: Found entity 1: 74175
Info: Elaborating entity "74175" for hierarchy "74175:inst45"
Info: Elaborated megafunction instantiation "74175:inst45"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/74292.bdf
    Info: Found entity 1: 74292
Info: Elaborating entity "74292" for hierarchy "74292:inst27"
Info: Elaborated megafunction instantiation "74292:inst27"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/74160.bdf
    Info: Found entity 1: 74160
Info: Elaborating entity "74160" for hierarchy "74160:inst7"
Info: Elaborated megafunction instantiation "74160:inst7"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/7408.bdf
    Info: Found entity 1: 7408
Info: Elaborating entity "7408" for hierarchy "7408:inst1"
Info: Elaborated megafunction instantiation "7408:inst1"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/74190.bdf
    Info: Found entity 1: 74190
Info: Elaborating entity "74190" for hierarchy "74190:inst6"
Info: Elaborated megafunction instantiation "74190:inst6"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/7402.bdf
    Info: Found entity 1: 7402
Info: Elaborating entity "7402" for hierarchy "7402:inst30"
Info: Elaborated megafunction instantiation "7402:inst30"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/others/maxplus2/7447.bdf
    Info: Found entity 1: 7447
Info: Elaborating entity "7447" for hierarchy "7447:inst"
Info: Elaborated megafunction instantiation "7447:inst"
Info: Ignored 22 buffer(s)
    Info: Ignored 22 SOFT buffer(s)
Warning: Reduced register "74160:inst7|9" with stuck data_in port to stuck value GND
Warning: Reduced register "74160:inst7|8" with stuck data_in port to stuck value GND
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
    Info: Register "74190:inst21|49" converted into equivalent circuit using register "74190:inst21|49~$emulated" and latch "74190:inst21|49~35"
    Info: Register "74190:inst21|50" converted into equivalent circuit using register "74190:inst21|50~$emulated" and latch "74190:inst21|50~37"
    Info: Register "74190:inst21|48" converted into equivalent circuit using register "74190:inst21|48~$emulated" and latch "74190:inst21|48~8"
    Info: Register "74190:inst24|48" converted into equivalent circuit using register "74190:inst24|48~$emulated" and latch "74190:inst24|48~8"
    Info: Register "74190:inst24|50" converted into equivalent circuit using register "74190:inst24|50~$emulated" and latch "74190:inst24|48~8"
    Info: Register "74190:inst33|49" converted into equivalent circuit using register "74190:inst33|49~$emulated" and latch "74190:inst24|48~8"
    Info: Register "74190:inst33|50" converted into equivalent circuit using register "74190:inst33|50~$emulated" and latch "74190:inst24|48~8"
    Info: Register "74190:inst33|48" converted into equivalent circuit using register "74190:inst33|48~$emulated" and latch "74190:inst24|48~8"
    Info: Register "74190:inst35|50" converted into equivalent circuit using register "74190:inst35|50~$emulated" and latch "74190:inst35|50~37"
    Info: Register "74190:inst35|48" converted into equivalent circuit using register "74190:inst35|48~$emulated" and latch "74190:inst35|50~37"
    Info: Register "74190:inst5|48" converted into equivalent circuit using register "74190:inst5|48~$emulated" and latch "74190:inst35|50~37"
    Info: Register "74190:inst5|49" converted into equivalent circuit using register "74190:inst5|49~$emulated" and latch "74190:inst35|50~37"
    Info: Register "74190:inst5|50" converted into equivalent circuit using register "74190:inst5|50~$emulated" and latch "74190:inst35|50~37"
    Info: Register "74190:inst6|48" converted into equivalent circuit using register "74190:inst6|48~$emulated" and latch "74190:inst6|48~8"
    Info: Register "74190:inst6|50" converted into equivalent circuit using register "74190:inst6|50~$emulated" and latch "74190:inst6|48~8"
Info: Implemented 207 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 34 output pins
    Info: Implemented 170 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Tue Dec 18 15:42:39 2007
    Info: Elapsed time: 00:00:09