app_init.ss

AMIS單晶片開發範本

// ---------------------------------------------------------------------------
// Copyright (c) 2008 Semiconductor Components Industries, LLC
// (d/b/a ON Semiconductor). All Rights Reserved.
//
// This code is the property of ON Semiconductor and may not be redistributed
// in any form without prior written permission from ON Semiconductor. The
// terms of use and warranty for this code are covered by contractual
// agreements between ON Semiconductor and the licensee.
// ---------------------------------------------------------------------------
// app_init.ss
// - Application-level initialization file
// ---------------------------------------------------------------------------
// $Revision: 1.16 $
// $Date: 2008/10/29 18:00:25 $
// ---------------------------------------------------------------------------
#include <sk25_hw.inc>
#include <boss.inc>
#include <bat.inc>
#include <bootloader.inc>
#include "app.inc"
#include <skfs.inc>
#include "Tone.inc"

    Mem_Start_Reloc_Segment(app_init_segment, SYSTEM_MEMORY_TYPE_P, 0x1000)

// ----------------------------------------------------------------------------
// Function:       App_Initialize
// Description:    Initialization routine for the application.
// ---------------------------------------------------------------------------
.global App_Initialize
App_Initialize:

    //
    // Configure interrupts
    //

    // Set up interrupt vectors
    Set_Int_Vect(D_VECT_WOLADONE, App_WOLA_ISR) 
    Set_Int_Vect(D_VECT_IOBLOCK, App_IOP_ISR)
    Set_Int_Vect(D_VECT_WATCHDOG, App_WATCHDOG_ISR)
    Set_Int_Vect(D_VECT_TIMER, Tone_TIMER_ISR)

    // Configure interrupt priorities
    Set_Int_Config(INT_CFG, INT_HIGHEST_PRIORITY)

    // Specify which interrupts are to be enabled
    Set_Int_Enable(INT_ENABLE_VAL)
    
    //
    // Configure the Watchdog timeout
    //  
    Set_Watchdog_Timeout(WATCHDOG_TIMEOUT)


    //
    // Configure analog blocks
    //
 
    // Configure voltage mode
    Write_AReg(A_PSU_CTRL, PSU_CFG)
    
    // Estimated delay of 50 ms for stabilization of the power supply.
    // The input to the Sys_Delay macro is in milliseconds, where the
    // macro assumes a system clock value of 1.28 MHz.
    // The system clock value has not yet been set but the calibrated
    // boot frequency is assumed to be 5.12 MHz.
    Sys_Delay(200)                      

    // Configure ADC current
    Write_AReg(A_ADC_CUR_CTRL, ADC_CTRL_CFG)

    // Configure DAC current and oversampling
    Write_AReg(A_DAC_CTRL, DAC_CTRL_CFG)

    // Configure input control
    Write_AReg(A_INPUT_CTRL, INPUT_CFG)
    
    // Configure the sample delay between the ADCs
    Write_AReg(A_DEL_INT_CTRL, SAMPLE_DELAY_INT_CFG)    
    Write_AReg(A_DEL_FRAC_CTRL, SAMPLE_DELAY_FRAC_CFG)      
    
    // Configure input filter
    Write_AReg(A_INFILT_CTRL, INFILT_CTRL_CFG)

    // Configure input gain
    Write_AReg(A_IN_GAIN_CTRL, IN_GAIN_CFG)

    // Calculate the input gain factor parameter SYS_CALC_GF for channel 0
    Calc_Gain_Factor_Val(SFVAR_CALCULATED, CH0_DF_GAIN)

    // Configure input gain factor (channel 0)
    Write_AReg(A_ADC_GF0_CTRL, SYS_CALC_GF)

    // Calculate the input gain factor parameter SYS_CALC_GF for channel 1
    Calc_Gain_Factor_Val(SFVAR_CALCULATED, CH1_DF_GAIN)

    // Configure input gain factor (channel 1)
    Write_AReg(A_ADC_GF1_CTRL, SYS_CALC_GF)

    // Configure output control
    Write_AReg(A_OUTPUT_CTRL, OUTPUT_CFG)

    // Configure output attenuation
    Write_AReg(A_OUT_ATTN_CTRL, OUT_ATT_CFG)
     

    //
    // Configure clocking
    //

    // Select which clocks are to be used
    Set_Clock_Select(CLK_EXTCLK, CLK_USRCLK)

    #if (CLOCKING_TYPE == CLOCKING_EXTERNAL)

        // Disable internal oscillator
        Write_AReg(A_CLK_CTRL, CLK_CTRL_CFG)
    
    #else

        // Check the bootloader and SDA are valid before using these
        // to configure the clock. This function will not exit if
        // either the bootloader or SDA are not valid.
        CALL App_Check_For_Valid_Bootloader_and_SDA

        // Since the application has returned from the function, the
        // bootloader and SDA must be valid.

        // Configure the internal oscillator
        // This will set A_CLK_CTRL and set the calibration value
        LDI AL, INTERNAL_OSC_CFG
        BL_SWITCH_FREQUENCY 
    
    #endif
   
    // Configure sampling frequency    
    Write_AReg(A_ADC_CTRL, SFVAR_CALCULATED)

    // Configure PCLK, MCLK and UCLK prescalers
    Set_Clock_Prescalers(CLK_CONFIG_PCLK, CLK_CONFIG_MCLK, CLK_CONFIG_USRCLK)

    // Configure WOLACLK prescaler
    LDI R4, D_WOLADIV_CFG
    LDI (R4), (CLK_CONFIG_WOLACLK)

   
    //
    // Application-specific initialization
    //
    
    // Configure GPIOs

    // Configure all pins as GPIOs 
    LDI R4, D_GPIO_PIN_CFG
    LDI (R4), GPIO_ENABLE_ALLGPIO
    
    // Configure GPIO pin directions
    LDI R4, D_GPIO_DIR_CFG
    LDI (R4), GPIO_DIR
    
    // Initialize variables

    // Initialize the WOLA state to idle
    LDSI A, WOLA_STATE_IDLE
    LD XL_WOLA_STATE, A, X

    // Clear all interrupt flags
    CLR AH
    LD XL_INTERRUPT_FLAGS, A, X


    // Clear the gain exponent
    CLR AH
    LDI R4, D_GAIN_EXP_DATA                 
    LD (R4), AH

    // Initialize the gains

    LDI R0, D_GAIN_BASE
    LDI AH, INITIAL_GAIN
    CLR AL

    // The gain for the first band must be written twice.
    // For odd stacking, this means writing the same value to both the 
    // real and imaginary locations.
    // For even stacking, this means specifying a value in both the
    // DC gain and Nyquist gain locations.
    LD (R0+), AH        
    LD (R0+), AH

    // Specify gains for the remaining bands.
    // The gain only needs to be written once.
    LDSI LC0, (NUM_BANDS-2)
init_gain_loop:
        LD (R0+), AH  // real
        LD (R0+), AL  // imaginary
    DBNZ0 init_gain_loop           

    // Configure the timer
    #if CLOCKING_TYPE == CLOCKING_INTERNAL
        // The PCLK is 1.28 MHz which results in Timer Clock = 10 kHz
        // TIMER DELAY, 400 ms, is expressed in terms of timer clock cycles, 
        // as 400 ms * Timer Clock = 400 ms * 10 kHz = 4000 = 0xFA0 (hex)
        Set_Timer(TIMER_PRESCALE_128, 0x0FA0, TIMER_FREERUN)
    #else
        // The PCLK is 1.536 MHz which results in Timer Clock = 12 kHz
        // TIMER DELAY, 400 ms, is expressed in terms of timer clock cycles, 
        // as 400 ms * Timer Clock = 400 ms * 12 kHz = 4800 = 0x12C0 (hex)
        // which is more than the maximum TIMER_DELAY value (4095 clock cycles)
        // Therefore, the TIMER_DELAY value is set to be 4092 in this case, which
        // corresponds to 341 ms at 12 kHz timer clock frequency
        Set_Timer(TIMER_PRESCALE_128, 0x0FFC, TIMER_FREERUN)
    #endif 
  
    // Start Timer
    Start_Timer
    
    RET R3
    
    
    
// ----------------------------------------------------------------------------
// Function:       App_Check_For_Valid_Bootloader_and_SDA
// Description:    Checks for a valid bootload and SDA.
// ---------------------------------------------------------------------------    
.global App_Check_For_Valid_Bootloader_and_SDA
App_Check_For_Valid_Bootloader_and_SDA:

    // Here the application tries to verify that there is a valid bootloader 
    // by checking the bootloader version returned by the bootloader that is  
    // run at start-up. Note that the application relies on a valid bootloader  
    // of at least version MIN_REQ_BOOTLOADER_VER (and a valid SDA) for  
    // correctly configuring the system clock. 

    // XL_BOOTLOADER_VERSION is in the reserved low X memory as specified
    // in boss.inc
    LD A, XL_BOOTLOADER_VERSION, X
    CMPI A, MIN_REQ_BOOTLOADER_VER 
    BRA bootload_error, NEG

    // If the bootloader version is ok, then we will verify that the bootloader 
    // had not returned a "bad SDA checksum" error number. This check is 
    // helpful especially when the application has been downloaded and run via 
    // the debugger instead of the bootloader.  
    LD A, XL_BOOTLOAD_ERRNUM, X
    CMPI A, SKFS_ERRNO_SDA_BAD_CHECKSUM
    BRA bootload_ok, NZ

bootload_error:
    // At this point it is clear that we don't have a valid bootloader or SDA 
    // in the EEPROM, meaning that the application itself will not be able to 
    // configure the system clock to a known, calibrated frequency. The 
    // execution at this point then simply configures GPIO 0 to output, and 
    // blinks GPIO 0 indefinitely.
    // 
    // When this happens, there is usually something wrong with the data
    // in the EEPROM. 
    // 
    // If you are not familiar with calibrating the system clock, downloading
    // the bootloader to the EEPROM, and configuring the SDA on the chips,
    // it is best to contact technical support at ON Semiconductor to resolve
    // this problem.
    //  
    // Only an experienced user of the chips should attempt to repair 
    // the problem by making sure that:
    // 1. a valid bootloader is stored in the EEPROM
    // 2. the SDA in the EEPROM contains valid clock calibration entries

    LDI R4, D_GPIO_PIN_CFG
    LDI (R4), GPIO_ENABLE_ALLGPIO
    LDI R4, D_GPIO_DIR_CFG
    RES (R4), 0

    LDI R4, D_GPIO_DATA

    // Here the application will blink GPIO 0 indefinitely. The speed at which
    // GPIO 0 is blinked depends on the actual system clock frequency. The
    // code here will toggle GPIO 0 every 1 second if the system clock is
    // approx. 1.28 MHz. GPIO 0 will blink faster if the actual clock frequency
    // is higher, and conversely slower if the actual clock frequency is lower.
gpio_blink:
    // turn on GPIO 0
    SET (R4), 0

    // then wait for a while (approx 1s)
    Sys_Delay(1000)

    // turn off GPIO 0
    RES (R4), 0

    // then wait for a while again (approx 1s)
    Sys_Delay(1000)

    // Repeat indefinitely - no Watchdog_Refresh is needed because it is
    // done in Sys_Delay
    BRA gpio_blink

bootload_ok:
    RET R3