readme.txt

AMIS單晶片開發範本

TONE GENERATION:
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The tone_generation sample demonstrates how to use the general-
purpose timer.  This code generates a 2 kHz tone that is mixed 
with the passthrough audio.  The tone is periodically switched 
on and off with interrupts from the general-purpose timer.

The timer expires at 400 ms intervals when clocking internally.
This is configured using 4000 timer cycles (because PCLK is 1.28 MHz
and the timer is prescaled by 128).  When clocking externally, 4800
timer cycles would be needed for a 400 ms timer interrupt interval
(the timer clock is 1.536 MHz / 128), but the timeout can be
configured to a maximum of only 4095 timer cycles, so 400 ms cannot
be achieved.  Therefore, the timer is configured for 4092 cycles,
resulting in a timer interrupt interval of 341 ms.

During runtime, the timer issues an interrupt and the processor
vectors to Tone_TIMER_ISR (in Tone_ISR.ss) where a flag called
YL_TONE_STATUS is toggled between TONE_ON and TONE_OFF.  This 
YL_TONE_STATUS flag is checked in WOLA_ISR after WOLA synthesis 
is completed.  If YL_TONE_STATUS is TONE_ON, then a tone is 
generated and added to the data already in the Output FIFO; 
otherwise, a tone is not generated.

A 2 kHz tone is generated by sequentially adding values from the
tone table (located at XH_TONE_TABLE) to the data in the smart
output FIFO.  The tone table contains 2 periods of a 2 kHz sine
sampled at 16 kHz (i.e. the table contains 16 samples of the
sine).  A pointer is used to point to the beginning of the block
of R samples to be extracted from the tone table.  Every time R
samples have been extracted from the tone table, the pointer is
updated to point to the beginning of the next block of R samples.
When the pointer reaches the end of the tone table, it will wrap 
around to the beginning.

Where applicable (see the source code), the SYS_CLK frequency required 
for this sample is 2.56 MHz when the code is configured for 
internal clocking, and 3.072 MHz when the code is configured for 
external clocking.  If you are using the debugger to run the sample, 
it is a good idea to use the debugger's clock configuration facilities 
(before running the application) to set up the clock in the same way as 
the application will at runtime.  Otherwise, running the application 
will cause the clocking configuration to change, which can affect 
the debug interface speed and cause the debugger to have connection 
problems.

For internal clocking, the bootloader is used to set the SYS_CLK
frequency to 2.56 MHz.  Therefore, the system's EEPROM must contain
an SDA containing a 2.56 MHz calibration value, and a bootloader of
at least version 2.7.02.

For external clocking, ensure that the Evaluation and Development 
Board is set up to deliver its on-board clock to the chip as the 
external clock.

This sample application uses the direct digital output, so you
must ensure that your listening device is connected to the
digital output. 

For more information about the firmware and hardware requirements, 
see the Introduction to Sample Code manual in the EDK.

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Copyright (c) 2008 Semiconductor Components Industries, LLC
(d/b/a ON Semiconductor).