readme.txt

AMIS單晶片開發範本

BAND EQUALIZATION:
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The BandEQ sample demonstrates how to apply a static gain vector
with the WOLA coprocessor.

The gain vector is defined in app_memory.ss. 
It contains the gain values for 16 bands, with 2 components per
band.  It is designed for even stacking, where the first gain 
value is applied to the DC band, the second to the Nyquist band,
then real and imaginary components of the subsequent bands follow. 
A change to a WOLA configuration that uses odd stacking would
require the gain table to be changed accordingly. For full details
about the gain vector implemented by this application, see the
16-band static equalizer section of the Sample Code Tutorial.

Since this table is static (i.e. it does not change during
runtime), there is no need to calculate anything in the gain
application routines.  The table containing the gains is copied
directly to the address D_GAIN_BASE, where the WOLA looks for
the gains to apply. 

Where applicable (see the source code), the SYS_CLK frequency required 
for this sample is 2.56 MHz when the code is configured for 
internal clocking, and 3.072 MHz when the code is configured for 
external clocking.  If you are using the debugger to run the sample, 
it is a good idea to use the debugger's clock configuration facilities 
(before running the application) to set up the clock in the same way as 
the application will at runtime.  Otherwise, running the application 
will cause the clocking configuration to change, which can affect 
the debug interface speed and cause the debugger to have connection 
problems.

For internal clocking, the bootloader is used to set the SYS_CLK
frequency to 2.56 MHz.  Therefore, the system's EEPROM must contain
an SDA containing a 2.56 MHz calibration value, and a bootloader of
at least version 2.7.02.

For external clocking, ensure that the Evaluation and Development 
Board is set up to deliver its on-board clock to the chip as the 
external clock.

This sample application uses the direct digital output, so you
must ensure that your listening device is connected to the
digital output. 

For more information about the firmware and hardware requirements, 
see the Introduction to Sample Code manual in the EDK.

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Copyright (c) 2008 Semiconductor Components Industries, LLC
(d/b/a ON Semiconductor).