ecog1.asm

使用CYAN单片机的ECOG1开发板连接SIM300C的GSM模块开发的短信收发程序.供UART和AT指令编程者参考

; =============================================================================
;
; CREATED by eCOG1k Configuration Compiler Version 2.0
; DATE 2007-7-28 10:18:49
;
; INPUT :
; D:/simcom/software/SIM300C/ecog1.cfg
;
; WARNING! Any changes made to this file will be lost when it is regenerated
;          by the eCOG1 Configuration Compiler
;
; =============================================================================

	MODULE ecog1
	.CODE
	.LARGE

	ORG	$??CSTARTUP_END

; Define symbols used in mmu initialisation
; Internal flash code area addresses
$??code_log     =    0
$??code_phy     =    0
$??code_siz     =    H'8000

$ecog1ConfigMMU:

; 	Clock Setup Notes
; 
; 	32kHz and 5 MHz xtal fitted
; 
; 	Possible peripheral clock sources are:
; 	 Low Ref
; 	 Low PLL
; 	 High Ref
; 	 High PLL
; 

; 	---------------------------------
; 	Configuring CPU and memory clocks
; 	---------------------------------
; 	Uart is using High PLL
; 	Dusart is using High PLL
; 	Sleep timeout is using High Ref
; 	Timers are using High PLL
;	in_clk source is High PLL

; 	Enable clocks
	ld	AH,#H'8001
	st	AH,@H'ff6c	; ssm.clk_en

;	CPU frequency > 10 MHz - inserting flash wait state
	ld	AH,#H'2
	st	AH,@H'ff67	; mmu.flash_ctrl

;	Setting prescalar and divider
	ld	AH,#H'37
	st	AH,@H'ff72	; ssm.cpu

;	Setting in_clk source
?LOOP1:
	ld	AH,#H'20
	st	AH,@H'ff74	; ssm.cfg

	ld	AL,@H'ff72	; ssm.cpu
	asr	#8
	and	AL,#15
	cmp	AL,#2
	bne	?LOOP1

; 	------------------------
; 	; Configure MMU (part 1)
; 	------------------------

; 	Setup MMU to enable cache configuration

	ld	x, #h'ff43		; mmu base pointer

; 	Map CodeFlash Physical 0 - 7fff to Logical Code 0 - 7fff
	ld	al, #h'0		
	st	al, @(1,x)		; mmu.xxx_log h'ff44
	st	al, @(2,x)		; mmu.xxx_phys h'ff45
	ld	al, #h'7f		
	st	al, @(3,x)		; mmu.xxx_size h'ff46

; 	Enable translations
	ld	al, #h'0		
	st	al, @(0,x)		; mmu.translate_enable

; 	Clear the address exception. These can be active when the software has
; 	done a self reset using the if_reset and cpu_reset bits.
	ld	al,#h'a		
	st	al,@h'ff69		; Clear status in mmu.address_exception

; 	-------------------
; 	Cache Configuration
; 	-------------------

; macro used for initialisation of cache banks
??MEMFILL	MACRO    start, length, value
		LOCAL    fill_loop
		ld       x, &start
		ld       al, &length
		ld       ah, &value
&fill_loop:	st       ah, @(0,x)
		add      x, #1
		sub      al, #1
		bne      &fill_loop
		ENDMAC

	ld	AH,#H'0		
	st	AH,@H'ff42		; Enable both Cache banks for data access

; 	Set physical mappings of cache banks
	ld	al, #h'10		; map cache bank 0 at 0x1000 - 0x11ff
	st	al, @h'ff59		; mmu.cache0_data_log
	ld	al, #h'12		; map cache bank 1 at 0x1200 - 0x13ff
	st	al, @h'ff5a		; mmu.cache1_data_log

; 	Map both cache banks in data space
	ld	al, @h'ff43		; read mmu.translate_en
	or	al, #h'180		; map both cache banks to data space
	st	al, @h'ff43		; set mmu.translate_en

; 	Invalidate cache contents
	??MEMFILL #h'1000, #h'100, #h'0		
	??MEMFILL #h'1100, #h'100, #h'8000		
	??MEMFILL #h'1200, #h'100, #h'0		
	??MEMFILL #h'1300, #h'100, #h'8000		

; 	Unmap both cache banks from data space
	ld	al, @h'ff43		; read mmu.translate_en
	and	al, #h'fe7f		; unmap both cache banks from data space
	st	al, @h'ff43		; set mmu.translate_en

; 	Enable cache memory
; 	Mode is 'One Way 512 Words'
	ld	AH,#H'10
	st	AH,@H'ff41	; 	; Configure Cache

	ld	AH,#H'3
	st	AH,@H'ff42	; 	; Enable Cache

; 	Wait for HW
	nop				; Three NOPs are required following
	nop				; the enable
	nop		

; 	------------------------
; 	Port configuration:
;	A	11
;	B	3
;	C	4
;	D	0	Unused
;	E	2
;	F	3
;	G	0	Unused
;	H	0	Unused
;	I	0	Unused
;	J	3
;	K	3
;	L	1
; 	------------------------

	ld	AH,#H'e23b
	st	AH,@H'ff9c	; port.sel1

	ld	AH,#H'7c0
	st	AH,@H'ff9d	; port.sel2

	ld	AH,#H'e37
	st	AH,@H'ff9e	; port.en

	ld	AH,#H'1c8
	st	AH,@H'ff9f	; port.dis

; 	-------------------
; 	;GPIO Configuration
; 	-------------------

	ld	AH,#H'0
	st	AH,@H'ffa5	; io.gp0_3_cfg

	st	AH,@H'ffa6	; io.gp4_7_cfg

	st	AH,@H'ffa7	; io.gp8_11_cfg

	st	AH,@H'ffa8	; io.gp12_15_cfg

	st	AH,@H'ffa9	; io.gp16_19_cfg

	st	AH,@H'ffaa	; io.gp20_23_cfg

	st	AH,@H'ffab	; io.gp24_27_cfg

	st	AH,@H'ffac	; io.gp28_cfg

	ld	AH,#H'5555
	st	AH,@H'ffad	; io.gp0_3_out

	st	AH,@H'ffae	; io.gp4_7_out

	ld	AH,#H'aa65
	st	AH,@H'ffaf	; io.gp8_11_out

	ld	AH,#H'aa66
	st	AH,@H'ffb0	; io.gp12_15_out

	ld	AH,#H'555a
	st	AH,@H'ffb1	; io.gp16_19_out

	ld	AH,#H'a565
	st	AH,@H'ffb2	; io.gp20_23_out

	ld	AH,#H'aaaa
	st	AH,@H'ffb3	; io.gp24_27_out

	ld	AH,#H'a
	st	AH,@H'ffb4	; io.gp28_out

; 	-----------------
; 	PIO Configuration
; 	-----------------

	ld	AH,#H'902
	st	AH,@H'ffa0	; io.p_cfg

; 	----------------------
; 	Configure MMU (part 2)
; 	----------------------

	ld	x, #h'ff43		; mmu base pointer

; 	Map DataFlash Physical 7800 - 7fff to Logical Data 0 - 7ff
	ld	al, #h'0		
	st	al, @(13,x)		; mmu.xxx_log h'ff50
	ld	al, #h'78		
	st	al, @(14,x)		; mmu.xxx_phys h'ff51
	ld	al, #h'7		
	st	al, @(15,x)		; mmu.xxx_size h'ff52

; 	Map DataRam0 Physical 0 - 7ff to Logical Data e800 - efff
	ld	al, #h'e8		
	st	al, @(16,x)		; mmu.xxx_log h'ff53
	ld	al, #h'0		
	st	al, @(17,x)		; mmu.xxx_phys h'ff54
	ld	al, #h'7		
	st	al, @(18,x)		; mmu.xxx_size h'ff55

; 	Enable translations
	ld	al, #h'10		
	st	al, @(0,x)		; mmu.translate_enable

; 	Clear the address exception. These can be active when the software has
; 	done a self reset using the if_reset and cpu_reset bits.
	ld	al,#h'a		
	st	al,@h'ff69		; Clear status in mmu.address_exception

	bra	$ecog1ConfigContinue

; 	------------------
; 	Main Configuration
; 	------------------

$ecog1Config:

; 	-----------------
; 	SPI Configuration
; 	-----------------

	; Setting up SPI on DUSART Channel A
	ld	AH,#H'9
	st	AH,@H'feb4	; dusart.a_cfg

	ld	AH,#H'8
	st	AH,@H'feb5	; dusart.a_smpl_cfg

	ld	AH,#H'202
	st	AH,@H'feb6	; dusart.a_sym_cfg

	ld	AH,#H'88
	st	AH,@H'feef	; dusart.spi_tx_cfg

	ld	AH,#H'aa
	st	AH,@H'fef0	; dusart.spi_rx_cfg

	ld	AH,#H'7070
	st	AH,@H'fef2	; dusart.spi_frame_ctrl

; 	-----------------
; 	I2C Configuration
; 	-----------------

	; Setting up I2C on DUSART Channel B
	ld	AH,#H'0
	st	AH,@H'fed0	; dusart.b_cfg

	st	AH,@H'fed1	; dusart.b_smpl_cfg

	st	AH,@H'fed2	; dusart.b_sym_cfg

	st	AH,@H'feee	; dusart.i2c_master_cmd

; 	Enable DUSART clock source

; 	Enable divider chain for DUSART
; 	Using High PLL
	ld	AH,#H'4
	st	AH,@H'ff6b	; ssm.rst_clr

; 	Select DUSART clock source
	ld	AH,@H'ff75		; ssm.div_sel
	and	AH,#B'1111011111111101	; clear DUSART selections
	or	AH,#H'2
	st	AH,@H'ff75

; 	Select DUSART Divider tap
	ld	AH,@H'ff76		; ssm.tap_sel1
	and	AH,#H'f0ff
	or	AH,#H'100
	st	AH,@H'ff76

; 	Enable DUSART clock
	ld	AH,#H'20
	st	AH,@H'ff6b	; ssm.rst_clr

	st	AH,@H'ff6c	; ssm.clk_en

; 	------------------------
; 	UART A & B Configuration
; 	------------------------

	ld	AH,#H'0
	st	AH,@H'fea1	; duart.frame_cfg

	st	AH,@H'fea2	; duart.a_tmr_cfg

	st	AH,@H'feab	; duart.b_tmr_cfg

; 	Configure DUART clock source

; 	Enable divider chain for DUART
; 	Using High PLL
	ld	AH,#H'4
	st	AH,@H'ff6b	; ssm.rst_clr

; 	Select DUART clock source
	ld	AH,@H'ff75		; ssm.div_sel
	and	AH,#B'1111101111111110	; clear DUART selections
	or	AH,#H'1
	st	AH,@H'ff75

; 	Select DUART Divider tap
	ld	AH,@H'ff76		; ssm.tap_sel1
	and	AH,#H'ff0f
	st	AH,@H'ff76

;	Setting UARTA baud rate to 4800 (actual = 4792.94, divider = 162)
	ld	AH,#H'a2
	st	AH,@H'fea3	; duart.a_baud

;	Setting UARTB baud rate to 9600 (actual = 9645.06, divider = 80)
	ld	AH,#H'50
	st	AH,@H'feac	; duart.b_baud

;	Enabling duart clocks
	ld	AH,#H'10
	st	AH,@H'ff6b	; ssm.rst_clr

	ld	AH,#H'18
	st	AH,@H'ff6c	; ssm.clk_en

;	Enabling duart tx/rx
	ld	AH,#H'145
	st	AH,@H'fea0	; duart.ctrl

; 	---------------------
; 	Counter Configuration
; 	---------------------

	ld	AH,#H'30d3
	st	AH,@H'ff21	; cnt1 load value

	ld	AH,#H'0
	st	AH,@H'ff22	; cnt1 compare value

	ld	AH,#H'4e1
	st	AH,@H'ff24	; cnt2 load value

	ld	AH,#H'0
	st	AH,@H'ff25	; cnt2 compare value

	st	AH,@H'ff23	; tim.cnt1_cfg

	st	AH,@H'ff26	; tim.cnt2_cfg

	ld	AH,#H'6
	st	AH,@H'ff1e	; auto reload

	st	AH,@H'ff1d	; load values

; 	-----------------
; 	PWM Configuration
; 	-----------------

	ld	AH,#H'0
	st	AH,@H'ff27	; pwm1 load value

	st	AH,@H'ff28	; pwm1 transition value

	st	AH,@H'ff29	; pwm1 config

	st	AH,@H'ff2a	; pwm2 load value

	st	AH,@H'ff2b	; pwm2 transition value

	st	AH,@H'ff2c	; pwm2 config

	ld	AH,#H'1e
	st	AH,@H'ff1e	; auto reload

; 	----------------------
; 	Watchdog Configuration
; 	----------------------

	ld	AH,#H'100
	st	AH,@H'ff2e	; watchdog load value

	ld	AH,#H'20
	st	AH,@H'ff1d	; load values

; 	--------------------
; 	Timers Configuration
; 	--------------------

; 	Enable Timers clock source

; 	Enable divider chain for Timers
	ld	AH,#H'8
	st	AH,@H'ff6b	; ssm.rst_clr

; 	Select Timers clock source
	ld	AH,@H'ff75		; ssm.div_sel
	and	AH,#B'1110111100000011	; clear clk selections
	or	AH,#H'30
	st	AH,@H'ff75

; 	Select Timers Divider tap
	ld	AH,@H'ff77		; ssm.tap_sel2
	and	AH,#H'ff00
	or	AH,#H'1
	st	AH,@H'ff77

	ld	AH,@H'ff78		; ssm.tap_sel3
	and	AH,#H'ff00
	or	AH,#H'60
	st	AH,@H'ff78

; 	Enable Timers clock
	ld	AH,#H'3c0
	st	AH,@H'ff6b	; ssm.rst_clr

	st	AH,@H'ff6c	; ssm.clk_en

; 	-------------------
; 	Sleep Configuration
; 	-------------------

; 	Select Sleep Timeout clock source
	ld	AH,@H'ff75		; ssm.div_sel
	and	AH,#B'1101111111111111	; clear Sleep timeout selections
	st	AH,@H'ff75

	ld	AH,@H'ff76		; ssm.tap_sel1
	and	AH,#H'fff0
	st	AH,@H'ff76

	rts		

	ENDMOD		

; 	-----------
; 	END OF FILE
; 	-----------