📄 gps_sim.xpv
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// Version : eCOG Assembler - V1.9 (build 5179)
// Title : "Code Table"
// Date : Wed Aug 01 11:52:17 2007
// Command Line : ecogasm -cmdfile qqtemp.cmd [ --map
// D:/simcom/software/SIM300C/internal.map -quiet
// D:/simcom/software/SIM300C/irq.asm qqpack.asm
// D:/simcom/software/SIM300C/temp/ecog1.asm
// D:/simcom/software/SIM300C/temp/main.asm
// D:/simcom/software/SIM300C/temp/cyan_base_driver.asm
// D:/simcom/software/SIM300C/temp/gps.asm
// D:/simcom/software/SIM300C/temp/key_scan.asm
// D:/simcom/software/SIM300C/out/GPS_SIM.lib -o
// D:/simcom/software/SIM300C/out/GPS_SIM ]
// ROM START ADDRESS 000000
// WORDSIZE 16
// BASE HEX : HEX
// CODE - Start Address H'0; Size H'315B
@000000 40E0 // bra $?cstart_code
@000004 007D // ex_debug DC $minimal_handler
@000005 007D // ex_tim_wdog_ufl DC $minimal_handler
@000006 0085 // ex_adr_err DC $address_error
@000007 007D // reserved DC $minimal_handler
@000008 007D // ex_tim DC $minimal_handler
@000009 007D // ex_reserved DC $minimal_handler
@00000A 007D // ex_usart_a DC $minimal_handler
@00000B 007D // ex_usart_b DC $minimal_handler
@00000C 094F // ex_uart_a DC $usr_ex_handler??
@00000D 007D // ex_uart_b DC $minimal_handler
@00000E 007D // int_tim_tmr_ufl DC $minimal_handler
@00000F 0542 // int_tim_cnt1_ufl DC $timer1_isr??
@000010 0587 // int_tim_cnt2_ufl DC $timer2_isr??
@000011 007D // int_tim_cnt1_match DC $minimal_handler
@000012 007D // int_tim_cnt2_match DC $minimal_handler
@000013 007D // int_tim_pwm1_ufl DC $minimal_handler
@000014 007D // int_tim_pwm2_ufl DC $minimal_handler
@000015 007D // int_tim_pwm1_match DC $minimal_handler
@000016 007D // int_tim_pwm2_match DC $minimal_handler
@000017 007D // int_tim_cap_ofl DC $minimal_handler
@000018 007D // int_tim_cap1 DC $minimal_handler
@000019 007D // int_tim_cap2 DC $minimal_handler
@00001A 007D // int_tim_cap3 DC $minimal_handler
@00001B 007D // int_tim_cap4 DC $minimal_handler
@00001C 007D // int_tim_cap5 DC $minimal_handler
@00001D 007D // int_tim_cap6 DC $minimal_handler
@00001E 007D // int_tim_ltmr_ufl DC $minimal_handler
@00001F 007D // int_reserved1 DC $minimal_handler
@000020 007D // int_reserved2 DC $minimal_handler
@000021 007D // int_reserved3 DC $minimal_handler
@000022 007D // int_reserved4 DC $minimal_handler
@000023 007D // int_reserved5 DC $minimal_handler
@000024 007D // int_reserved6 DC $minimal_handler
@000025 007D // int_reserved7 DC $minimal_handler
@000026 007D // int_reserved8 DC $minimal_handler
@000027 007D // int_usart_a_rx DC $minimal_handler
@000028 007D // int_usart_a_tx DC $minimal_handler
@000029 007D // int_usart_b_rx DC $minimal_handler
@00002A 007D // int_usart_b_tx DC $minimal_handler
@00002B 007D // int_sci_tx_done DC $minimal_handler
@00002C 007D // int_sci_tx_err DC $minimal_handler
@00002D 007D // int_sci DC $minimal_handler
@00002E 007D // int_ifr_tx_done DC $minimal_handler
@00002F 007D // int_ifr_rx_done DC $minimal_handler
@000030 007D // int_ifr_rx_err DC $minimal_handler
@000031 007D // int_ifr_frame_done DC $minimal_handler
@000032 05DB // int_uart_a_tx_rdy DC $usra_tx_handler??
@000033 0893 // int_uart_a_rx_rdy DC $usr_rx_handler??
@000034 05CC // int_uart_b_tx_rdy DC $usrb_tx_handler??
@000035 007D // int_uart_b_rx_rdy DC $minimal_handler
@000036 007D // int_ehi DC $minimal_handler
@000037 007D // int_gpio DC $minimal_handler
@000038 007D // int_adc DC $minimal_handler
@000040 54E0 // bra $ecog1ConfigMMU
@000041 EE00 // ld x, #$??HEAP
@000042 F818
@000043 0100 // ld al, #$??HEAP_SIZE
@000044 8014
@000045 9A00 // ld ah, #h'9999
@000046 9910
@000047 0022 // $??0000: st ah, @(0,x)
@000048 0138 // add x, #1
@000049 0154 // sub al, #1
@00004A FDF0 // bne $??0000
@00004B EE00 // ld x, #$??STACK
@00004C 7818
@00004D 0100 // ld al, #$??STACK_SIZE
@00004E 0014
@00004F AB00 // ld ah, #h'AAAA
@000050 AA10
@000051 0022 // $??0001: st ah, @(0,x)
@000052 0138 // add x, #1
@000053 0154 // sub al, #1
@000054 FDF0 // bne $??0001
@000055 EF00 // ld x, #$??ISTACK
@000056 7818
@000057 4014 // ld al, #$??ISTACK_SIZE
@000058 BC00 // ld ah, #h'BBBB
@000059 BB10
@00005A 0022 // $??0002: st ah, @(0,x)
@00005B 0138 // add x, #1
@00005C 0154 // sub al, #1
@00005D FDF0 // bne $??0002
@00005E 0118 // ld x, #$??INITC
@00005F ED00 // ld y, #$??INIT
@000060 A11C
@000061 0214 // ld al, #$??INITC_SIZE
@000062 FF09 // bc
@000063 ED00 // ld x, #$??VAR
@000064 A318
@000065 0100 // ld al, #$??VAR_SIZE
@000066 5514
@000067 0010 // ld ah, #h'0
@000068 0022 // $??0003: st ah, @(0,x)
@000069 0138 // add x, #1
@00006A 0154 // sub al, #1
@00006B FDF0 // bne $??0003
@00006C F000 // ld y, #IY_SCRATCH
@00006D E01C
@00006E FF01 // st flags, @(-1,y)
@00006F FF17 // ld al, @(-1,y)
@000070 10B4 // or al, #h'10
@000071 FF27 // st al, @(-1,y)
@000072 FF05 // ld flags, @(-1,y)
@000073 EF00 // ld y, #$??STACK_HI
@000074 771C
@000075 0100 // bsr $ecog1Config
@000076 C49C
@000077 0310 // ld ah, #argv
@000078 0014 // ld al, #0
@000079 0100 // bsr $main
@00007A 769C
@00007B 0004 // brk
@00007C 84E0 // bra 0
@00007D DF01 // st flags,@(-33,y)
@00007E DE27 // st al, @(-34,y)
@00007F DF17 // ld al, @(-33,y)
@000080 10B4 // or al, #h'0010
@000081 DF27 // st al, @(-33,y)
@000082 0004 // brk
@000083 DE17 // ld al, @(-34,y)
@000084 DF0D // rti @(-33,y)
@000085 DF01 // st flags,@(-33,y)
@000086 DE27 // st al, @(-34,y)
@000087 DF17 // ld al, @(-33,y)
@000088 10B4 // or al, #h'0010
@000089 DF27 // st al, @(-33,y)
@00008A 0004 // brk
@00008B 0A14 // ld al, #h'a
@00008C FF00 // st al, @h'ff69
@00008D 6925
@00008E 0200 // ld al, #h'200
@00008F 0014
@000090 FF00 // st al, @h'ff7a
@000091 7A25
@000092 DE17 // ld al, @(-34,y)
@000093 DF0D // rti @(-33,y)
@000094 8000 // ld AH,#H'8001
@000095 0110
@000096 FF00 // st AH,@H'ff6c
@000097 6C21
@000098 0210 // ld AH,#H'2
@000099 FF00 // st AH,@H'ff67
@00009A 6721
@00009B 3710 // ld AH,#H'37
@00009C FF00 // st AH,@H'ff72
@00009D 7221
@00009E 2010 // ld AH,#H'20
@00009F FF00 // st AH,@H'ff74
@0000A0 7421
@0000A1 FF00 // ld AL,@H'ff72
@0000A2 7215
@0000A3 08A4 // asr #8
@0000A4 0FC4 // and AL,#15
@0000A5 0284 // cmp AL,#2
@0000A6 F8F0 // bne ?LOOP1
@0000A7 FF00 // ld x, #h'ff43
@0000A8 4318
@0000A9 0014 // ld al, #h'0
@0000AA 0126 // st al, @(1,x)
@0000AB 0226 // st al, @(2,x)
@0000AC 7F14 // ld al, #h'7f
@0000AD 0326 // st al, @(3,x)
@0000AE 0014 // ld al, #h'0
@0000AF 0026 // st al, @(0,x)
@0000B0 0A14 // ld al,#h'a
@0000B1 FF00 // st al,@h'ff69
@0000B2 6925
@0000B3 0010 // ld AH,#H'0
@0000B4 FF00 // st AH,@H'ff42
@0000B5 4221
@0000B6 1014 // ld al, #h'10
@0000B7 FF00 // st al, @h'ff59
@0000B8 5925
@0000B9 1214 // ld al, #h'12
@0000BA FF00 // st al, @h'ff5a
@0000BB 5A25
@0000BC FF00 // ld al, @h'ff43
@0000BD 4315
@0000BE 0200 // or al, #h'180
@0000BF 80B4
@0000C0 FF00 // st al, @h'ff43
@0000C1 4325
@0000C2 1000 // ld x, #h'1000
@0000C3 0018
@0000C4 0100 // ld al, #h'100
@0000C5 0014
@0000C6 0010 // ld ah, #h'0
@0000C7 0022 // $??0004: st ah, @(0,x)
@0000C8 0138 // add x, #1
@0000C9 0154 // sub al, #1
@0000CA FDF0 // bne $??0004
@0000CB 1100 // ld x, #h'1100
@0000CC 0018
@0000CD 0100 // ld al, #h'100
@0000CE 0014
@0000CF 8000 // ld ah, #h'8000
@0000D0 0010
@0000D1 0022 // $??0005: st ah, @(0,x)
@0000D2 0138 // add x, #1
@0000D3 0154 // sub al, #1
@0000D4 FDF0 // bne $??0005
@0000D5 1200 // ld x, #h'1200
@0000D6 0018
@0000D7 0100 // ld al, #h'100
@0000D8 0014
@0000D9 0010 // ld ah, #h'0
@0000DA 0022 // $??0006: st ah, @(0,x)
@0000DB 0138 // add x, #1
@0000DC 0154 // sub al, #1
@0000DD FDF0 // bne $??0006
@0000DE 1300 // ld x, #h'1300
@0000DF 0018
@0000E0 0100 // ld al, #h'100
@0000E1 0014
@0000E2 8000 // ld ah, #h'8000
@0000E3 0010
@0000E4 0022 // $??0007: st ah, @(0,x)
@0000E5 0138 // add x, #1
@0000E6 0154 // sub al, #1
@0000E7 FDF0 // bne $??0007
@0000E8 FF00 // ld al, @h'ff43
@0000E9 4315
@0000EA FE00 // and al, #h'fe7f
@0000EB 7FC4
@0000EC FF00 // st al, @h'ff43
@0000ED 4325
@0000EE 1010 // ld AH,#H'10
@0000EF FF00 // st AH,@H'ff41
@0000F0 4121
@0000F1 0310 // ld AH,#H'3
@0000F2 FF00 // st AH,@H'ff42
@0000F3 4221
@0000F4 0000 // nop
@0000F5 0000 // nop
@0000F6 0000 // nop
@0000F7 E200 // ld AH,#H'e23b
@0000F8 3B10
@0000F9 9C21 // st AH,@H'ff9c
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