📄 segment7.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "count\[24\] " "Info: Detected ripple clock \"count\[24\]\" as buffer" { } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "count\[24\]" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register TEMP\[2\]~278 register TEMP\[3\]~280 339.1 MHz 2.949 ns Internal " "Info: Clock \"clk\" has Internal fmax of 339.1 MHz between source register \"TEMP\[2\]~278\" and destination register \"TEMP\[3\]~280\" (period= 2.949 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.730 ns + Longest register register " "Info: + Longest register to register delay is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TEMP\[2\]~278 1 REG LCFF_X27_Y1_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y1_N7; Fanout = 1; REG Node = 'TEMP\[2\]~278'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { TEMP[2]~278 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.502 ns) + CELL(0.428 ns) 0.930 ns TEMP\[2\]~279 2 COMB LCCOMB_X27_Y1_N2 10 " "Info: 2: + IC(0.502 ns) + CELL(0.428 ns) = 0.930 ns; Loc. = LCCOMB_X27_Y1_N2; Fanout = 10; COMB Node = 'TEMP\[2\]~279'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.930 ns" { TEMP[2]~278 TEMP[2]~279 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.417 ns) 1.825 ns add~377 3 COMB LCCOMB_X27_Y1_N24 1 " "Info: 3: + IC(0.478 ns) + CELL(0.417 ns) = 1.825 ns; Loc. = LCCOMB_X27_Y1_N24; Fanout = 1; COMB Node = 'add~377'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.895 ns" { TEMP[2]~279 add~377 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.418 ns) 2.243 ns add~378 4 COMB LCCOMB_X27_Y1_N26 1 " "Info: 4: + IC(0.000 ns) + CELL(0.418 ns) = 2.243 ns; Loc. = LCCOMB_X27_Y1_N26; Fanout = 1; COMB Node = 'add~378'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.418 ns" { add~377 add~378 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.153 ns) 2.644 ns TEMP\[3\]~285 5 COMB LCCOMB_X27_Y1_N12 1 " "Info: 5: + IC(0.248 ns) + CELL(0.153 ns) = 2.644 ns; Loc. = LCCOMB_X27_Y1_N12; Fanout = 1; COMB Node = 'TEMP\[3\]~285'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.401 ns" { add~378 TEMP[3]~285 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.730 ns TEMP\[3\]~280 6 REG LCFF_X27_Y1_N13 1 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.730 ns; Loc. = LCFF_X27_Y1_N13; Fanout = 1; REG Node = 'TEMP\[3\]~280'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.086 ns" { TEMP[3]~285 TEMP[3]~280 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.502 ns 55.02 % " "Info: Total cell delay = 1.502 ns ( 55.02 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.228 ns 44.98 % " "Info: Total interconnect delay = 1.228 ns ( 44.98 % )" { } { } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "2.730 ns" { TEMP[2]~278 TEMP[2]~279 add~377 add~378 TEMP[3]~285 TEMP[3]~280 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { TEMP[2]~278 TEMP[2]~279 add~377 add~378 TEMP[3]~285 TEMP[3]~280 } { 0.000ns 0.502ns 0.478ns 0.000ns 0.248ns 0.000ns } { 0.000ns 0.428ns 0.417ns 0.418ns 0.153ns 0.086ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.989 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { clk } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'clk~clkctrl'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(0.803 ns) 2.934 ns count\[24\] 3 REG LCFF_X64_Y19_N25 2 " "Info: 3: + IC(1.068 ns) + CELL(0.803 ns) = 2.934 ns; Loc. = LCFF_X64_Y19_N25; Fanout = 2; REG Node = 'count\[24\]'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "1.871 ns" { clk~clkctrl count[24] } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.000 ns) 3.368 ns count\[24\]~clkctrl 4 COMB CLKCTRL_G4 4 " "Info: 4: + IC(0.434 ns) + CELL(0.000 ns) = 3.368 ns; Loc. = CLKCTRL_G4; Fanout = 4; COMB Node = 'count\[24\]~clkctrl'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.434 ns" { count[24] count[24]~clkctrl } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.548 ns) 4.989 ns TEMP\[3\]~280 5 REG LCFF_X27_Y1_N13 1 " "Info: 5: + IC(1.073 ns) + CELL(0.548 ns) = 4.989 ns; Loc. = LCFF_X27_Y1_N13; Fanout = 1; REG Node = 'TEMP\[3\]~280'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "1.621 ns" { count[24]~clkctrl TEMP[3]~280 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.296 ns 46.02 % " "Info: Total cell delay = 2.296 ns ( 46.02 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.693 ns 53.98 % " "Info: Total interconnect delay = 2.693 ns ( 53.98 % )" { } { } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[3]~280 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[3]~280 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.989 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 4.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { clk } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'clk~clkctrl'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(0.803 ns) 2.934 ns count\[24\] 3 REG LCFF_X64_Y19_N25 2 " "Info: 3: + IC(1.068 ns) + CELL(0.803 ns) = 2.934 ns; Loc. = LCFF_X64_Y19_N25; Fanout = 2; REG Node = 'count\[24\]'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "1.871 ns" { clk~clkctrl count[24] } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.000 ns) 3.368 ns count\[24\]~clkctrl 4 COMB CLKCTRL_G4 4 " "Info: 4: + IC(0.434 ns) + CELL(0.000 ns) = 3.368 ns; Loc. = CLKCTRL_G4; Fanout = 4; COMB Node = 'count\[24\]~clkctrl'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.434 ns" { count[24] count[24]~clkctrl } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.548 ns) 4.989 ns TEMP\[2\]~278 5 REG LCFF_X27_Y1_N7 1 " "Info: 5: + IC(1.073 ns) + CELL(0.548 ns) = 4.989 ns; Loc. = LCFF_X27_Y1_N7; Fanout = 1; REG Node = 'TEMP\[2\]~278'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "1.621 ns" { count[24]~clkctrl TEMP[2]~278 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.296 ns 46.02 % " "Info: Total cell delay = 2.296 ns ( 46.02 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.693 ns 53.98 % " "Info: Total interconnect delay = 2.693 ns ( 53.98 % )" { } { } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[3]~280 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[3]~280 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" { } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "2.730 ns" { TEMP[2]~278 TEMP[2]~279 add~377 add~378 TEMP[3]~285 TEMP[3]~280 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { TEMP[2]~278 TEMP[2]~279 add~377 add~378 TEMP[3]~285 TEMP[3]~280 } { 0.000ns 0.502ns 0.478ns 0.000ns 0.248ns 0.000ns } { 0.000ns 0.428ns 0.417ns 0.418ns 0.153ns 0.086ns } } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[3]~280 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[3]~280 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "TEMP\[2\]~278 sw17 clk 5.061 ns register " "Info: tsu for register \"TEMP\[2\]~278\" (data pin = \"sw17\", clock pin = \"clk\") is 5.061 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.086 ns + Longest pin register " "Info: + Longest pin to register delay is 10.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.805 ns) 0.805 ns sw17 1 PIN PIN_V2 15 " "Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_V2; Fanout = 15; PIN Node = 'sw17'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { sw17 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.551 ns) 7.356 ns TEMP\[0\]~37 2 COMB LOOP LCCOMB_X27_Y1_N16 9 " "Info: 2: + IC(0.000 ns) + CELL(6.551 ns) = 7.356 ns; Loc. = LCCOMB_X27_Y1_N16; Fanout = 9; COMB LOOP Node = 'TEMP\[0\]~37'" { { "Info" "ITDB_PART_OF_SCC" "TEMP\[0\]~37 LCCOMB_X27_Y1_N16 " "Info: Loc. = LCCOMB_X27_Y1_N16; Node \"TEMP\[0\]~37\"" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { TEMP[0]~37 } "NODE_NAME" } "" } } } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { TEMP[0]~37 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "6.551 ns" { sw17 TEMP[0]~37 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.447 ns) 8.131 ns TEMP\[1\]~277 3 COMB LCCOMB_X27_Y1_N28 10 " "Info: 3: + IC(0.328 ns) + CELL(0.447 ns) = 8.131 ns; Loc. = LCCOMB_X27_Y1_N28; Fanout = 10; COMB Node = 'TEMP\[1\]~277'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.775 ns" { TEMP[0]~37 TEMP[1]~277 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.475 ns) + CELL(0.417 ns) 9.023 ns add~375 4 COMB LCCOMB_X27_Y1_N22 2 " "Info: 4: + IC(0.475 ns) + CELL(0.417 ns) = 9.023 ns; Loc. = LCCOMB_X27_Y1_N22; Fanout = 2; COMB Node = 'add~375'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.892 ns" { TEMP[1]~277 add~375 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.418 ns) 9.441 ns add~376 5 COMB LCCOMB_X27_Y1_N24 1 " "Info: 5: + IC(0.000 ns) + CELL(0.418 ns) = 9.441 ns; Loc. = LCCOMB_X27_Y1_N24; Fanout = 1; COMB Node = 'add~376'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.418 ns" { add~375 add~376 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.279 ns) + CELL(0.280 ns) 10.000 ns TEMP\[2\]~284 6 COMB LCCOMB_X27_Y1_N6 1 " "Info: 6: + IC(0.279 ns) + CELL(0.280 ns) = 10.000 ns; Loc. = LCCOMB_X27_Y1_N6; Fanout = 1; COMB Node = 'TEMP\[2\]~284'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.559 ns" { add~376 TEMP[2]~284 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 10.086 ns TEMP\[2\]~278 7 REG LCFF_X27_Y1_N7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 10.086 ns; Loc. = LCFF_X27_Y1_N7; Fanout = 1; REG Node = 'TEMP\[2\]~278'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.086 ns" { TEMP[2]~284 TEMP[2]~278 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.004 ns 89.27 % " "Info: Total cell delay = 9.004 ns ( 89.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.082 ns 10.73 % " "Info: Total interconnect delay = 1.082 ns ( 10.73 % )" { } { } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "10.086 ns" { sw17 TEMP[0]~37 TEMP[1]~277 add~375 add~376 TEMP[2]~284 TEMP[2]~278 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.086 ns" { sw17 sw17~combout TEMP[0]~37 TEMP[1]~277 add~375 add~376 TEMP[2]~284 TEMP[2]~278 } { 0.000ns 0.000ns 0.000ns 0.328ns 0.475ns 0.000ns 0.279ns 0.000ns } { 0.000ns 0.805ns 6.551ns 0.447ns 0.417ns 0.418ns 0.280ns 0.086ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.989 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 4.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { clk } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'clk~clkctrl'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(0.803 ns) 2.934 ns count\[24\] 3 REG LCFF_X64_Y19_N25 2 " "Info: 3: + IC(1.068 ns) + CELL(0.803 ns) = 2.934 ns; Loc. = LCFF_X64_Y19_N25; Fanout = 2; REG Node = 'count\[24\]'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "1.871 ns" { clk~clkctrl count[24] } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.000 ns) 3.368 ns count\[24\]~clkctrl 4 COMB CLKCTRL_G4 4 " "Info: 4: + IC(0.434 ns) + CELL(0.000 ns) = 3.368 ns; Loc. = CLKCTRL_G4; Fanout = 4; COMB Node = 'count\[24\]~clkctrl'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "0.434 ns" { count[24] count[24]~clkctrl } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.548 ns) 4.989 ns TEMP\[2\]~278 5 REG LCFF_X27_Y1_N7 1 " "Info: 5: + IC(1.073 ns) + CELL(0.548 ns) = 4.989 ns; Loc. = LCFF_X27_Y1_N7; Fanout = 1; REG Node = 'TEMP\[2\]~278'" { } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "1.621 ns" { count[24]~clkctrl TEMP[2]~278 } "NODE_NAME" } "" } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.296 ns 46.02 % " "Info: Total cell delay = 2.296 ns ( 46.02 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.693 ns 53.98 % " "Info: Total interconnect delay = 2.693 ns ( 53.98 % )" { } { } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } } 0} } { { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "10.086 ns" { sw17 TEMP[0]~37 TEMP[1]~277 add~375 add~376 TEMP[2]~284 TEMP[2]~278 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.086 ns" { sw17 sw17~combout TEMP[0]~37 TEMP[1]~277 add~375 add~376 TEMP[2]~284 TEMP[2]~278 } { 0.000ns 0.000ns 0.000ns 0.328ns 0.475ns 0.000ns 0.279ns 0.000ns } { 0.000ns 0.805ns 6.551ns 0.447ns 0.417ns 0.418ns 0.280ns 0.086ns } } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "4.989 ns" { clk clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.989 ns" { clk clk~combout clk~clkctrl count[24] count[24]~clkctrl TEMP[2]~278 } { 0.000ns 0.000ns 0.118ns 1.068ns 0.434ns 1.073ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } } 0}
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