segment7.tan.qmsg

7段数码管译码器,用VHDL在FPGA2000上显示

{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "TEMP\[0\]~37 " "Warning: Node \"TEMP\[0\]~37\" is a latch" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "TEMP\[0\]~37 " "Info: Node \"TEMP\[0\]~37\"" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } }  } 0}  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}