segment7.fit.qmsg

7段数码管译码器,用VHDL在FPGA2000上显示

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F672C6 " "Warning: Timing characteristics of device EP2C35F672C6 are preliminary" {  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "15 " "Warning: Found 15 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[0\] 0 " "Warning: Pin \"hex0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[1\] 0 " "Warning: Pin \"hex0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[2\] 0 " "Warning: Pin \"hex0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[3\] 0 " "Warning: Pin \"hex0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[4\] 0 " "Warning: Pin \"hex0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[5\] 0 " "Warning: Pin \"hex0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex0\[6\] 0 " "Warning: Pin \"hex0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[0\] 0 " "Warning: Pin \"hex1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[1\] 0 " "Warning: Pin \"hex1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[2\] 0 " "Warning: Pin \"hex1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[3\] 0 " "Warning: Pin \"hex1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[4\] 0 " "Warning: Pin \"hex1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[5\] 0 " "Warning: Pin \"hex1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "hex1\[6\] 0 " "Warning: Pin \"hex1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led17 0 " "Warning: Pin \"led17\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "hex1\[1\] GND " "Info: Pin hex1\[1\] has GND driving its datain port" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "hex1\[1\]" } } } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { hex1[1] } "NODE_NAME" } "" } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.fld" "" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.fld" "" "" { hex1[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "hex1\[2\] GND " "Info: Pin hex1\[2\] has GND driving its datain port" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "hex1\[2\]" } } } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { hex1[2] } "NODE_NAME" } "" } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.fld" "" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.fld" "" "" { hex1[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "hex1\[6\] VCC " "Info: Pin hex1\[6\] has VCC driving its datain port" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "hex1\[6\]" } } } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7_cmp.qrpt" Compiler "segment7" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/evelyn/ex (4)/db/segment7.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/" "" "" { hex1[6] } "NODE_NAME" } "" } } { "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.fld" "" { Floorplan "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.fld" "" "" { hex1[6] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 18 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 28 15:54:04 2007 " "Info: Processing ended: Wed Nov 28 15:54:04 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}