segment7.tan.rpt

7段数码管译码器,用VHDL在FPGA2000上显示

; N/A   ; None         ; 9.761 ns   ; TEMP[1]~276 ; hex0[1] ; clk        ;
; N/A   ; None         ; 9.757 ns   ; TEMP[1]~276 ; hex0[0] ; clk        ;
; N/A   ; None         ; 9.596 ns   ; TEMP[3]~280 ; hex0[3] ; clk        ;
; N/A   ; None         ; 9.594 ns   ; TEMP[3]~280 ; hex0[5] ; clk        ;
; N/A   ; None         ; 9.590 ns   ; TEMP[3]~280 ; hex0[6] ; clk        ;
; N/A   ; None         ; 9.590 ns   ; TEMP[3]~280 ; hex0[4] ; clk        ;
+-------+--------------+------------+-------------+---------+------------+


+--------------------------------------------------------------+
; tpd                                                          ;
+-------+-------------------+-----------------+------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To      ;
+-------+-------------------+-----------------+------+---------+
; N/A   ; None              ; 13.786 ns       ; sw17 ; hex1[0] ;
; N/A   ; None              ; 13.638 ns       ; sw17 ; hex1[5] ;
; N/A   ; None              ; 13.178 ns       ; sw17 ; hex1[4] ;
; N/A   ; None              ; 13.178 ns       ; sw17 ; hex1[3] ;
; N/A   ; None              ; 13.107 ns       ; key3 ; hex1[0] ;
; N/A   ; None              ; 12.959 ns       ; key3 ; hex1[5] ;
; N/A   ; None              ; 12.499 ns       ; key3 ; hex1[4] ;
; N/A   ; None              ; 12.499 ns       ; key3 ; hex1[3] ;
; N/A   ; None              ; 12.443 ns       ; sw17 ; hex0[2] ;
; N/A   ; None              ; 12.440 ns       ; sw17 ; hex0[1] ;
; N/A   ; None              ; 12.432 ns       ; sw17 ; hex0[0] ;
; N/A   ; None              ; 12.188 ns       ; sw17 ; hex0[4] ;
; N/A   ; None              ; 12.188 ns       ; sw17 ; hex0[3] ;
; N/A   ; None              ; 12.186 ns       ; sw17 ; hex0[6] ;
; N/A   ; None              ; 12.184 ns       ; sw17 ; hex0[5] ;
; N/A   ; None              ; 11.623 ns       ; key3 ; hex0[2] ;
; N/A   ; None              ; 11.382 ns       ; key3 ; hex0[1] ;
; N/A   ; None              ; 11.374 ns       ; key3 ; hex0[0] ;
; N/A   ; None              ; 11.367 ns       ; key3 ; hex0[3] ;
; N/A   ; None              ; 11.364 ns       ; key3 ; hex0[5] ;
; N/A   ; None              ; 11.360 ns       ; key3 ; hex0[6] ;
; N/A   ; None              ; 11.360 ns       ; key3 ; hex0[4] ;
; N/A   ; None              ; 9.294 ns        ; sw17 ; led17   ;
+-------+-------------------+-----------------+------+---------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; 1.814 ns  ; key3 ; TEMP[3]~280 ; clk      ;
; N/A           ; None        ; 1.809 ns  ; key3 ; TEMP[1]~276 ; clk      ;
; N/A           ; None        ; 1.621 ns  ; key3 ; TEMP[0]~273 ; clk      ;
; N/A           ; None        ; 1.620 ns  ; key3 ; TEMP[2]~278 ; clk      ;
; N/A           ; None        ; -2.404 ns ; sw17 ; TEMP[3]~280 ; clk      ;
; N/A           ; None        ; -2.685 ns ; sw17 ; TEMP[1]~276 ; clk      ;
; N/A           ; None        ; -2.839 ns ; sw17 ; TEMP[2]~278 ; clk      ;
; N/A           ; None        ; -3.067 ns ; sw17 ; TEMP[0]~273 ; clk      ;
+---------------+-------------+-----------+------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
    Info: Processing started: Wed Nov 28 15:54:17 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off segment7 -c segment7 --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "TEMP[0]~37" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "TEMP[0]~37"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "count[24]" as buffer
Info: Clock "clk" has Internal fmax of 339.1 MHz between source register "TEMP[2]~278" and destination register "TEMP[3]~280" (period= 2.949 ns)
    Info: + Longest register to register delay is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y1_N7; Fanout = 1; REG Node = 'TEMP[2]~278'
        Info: 2: + IC(0.502 ns) + CELL(0.428 ns) = 0.930 ns; Loc. = LCCOMB_X27_Y1_N2; Fanout = 10; COMB Node = 'TEMP[2]~279'
        Info: 3: + IC(0.478 ns) + CELL(0.417 ns) = 1.825 ns; Loc. = LCCOMB_X27_Y1_N24; Fanout = 1; COMB Node = 'add~377'
        Info: 4: + IC(0.000 ns) + CELL(0.418 ns) = 2.243 ns; Loc. = LCCOMB_X27_Y1_N26; Fanout = 1; COMB Node = 'add~378'
        Info: 5: + IC(0.248 ns) + CELL(0.153 ns) = 2.644 ns; Loc. = LCCOMB_X27_Y1_N12; Fanout = 1; COMB Node = 'TEMP[3]~285'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.730 ns; Loc. = LCFF_X27_Y1_N13; Fanout = 1; REG Node = 'TEMP[3]~280'
        Info: Total cell delay = 1.502 ns ( 55.02 % )
        Info: Total interconnect delay = 1.228 ns ( 44.98 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 4.989 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.068 ns) + CELL(0.803 ns) = 2.93