lcok.tan.rpt

数字密码锁:S0是复位状态：密码为00000001

; N/A   ; None         ; 3.536 ns   ; code[3] ; temp[3]  ; key      ;
; N/A   ; None         ; 3.429 ns   ; code[6] ; temp[6]  ; key      ;
; N/A   ; None         ; 0.702 ns   ; code[1] ; state.s0 ; key      ;
; N/A   ; None         ; 0.544 ns   ; code[2] ; state.s0 ; key      ;
; N/A   ; None         ; 0.393 ns   ; code[0] ; state.s0 ; key      ;
; N/A   ; None         ; 0.124 ns   ; code[1] ; state.s1 ; key      ;
; N/A   ; None         ; -0.030 ns  ; change  ; state.s0 ; key      ;
; N/A   ; None         ; -0.030 ns  ; change  ; state.s2 ; key      ;
; N/A   ; None         ; -0.034 ns  ; code[2] ; state.s1 ; key      ;
; N/A   ; None         ; -0.185 ns  ; code[0] ; state.s1 ; key      ;
; N/A   ; None         ; -0.732 ns  ; code[1] ; temp[1]  ; key      ;
; N/A   ; None         ; -0.863 ns  ; code[2] ; temp[2]  ; key      ;
; N/A   ; None         ; -0.988 ns  ; code[0] ; temp[0]  ; key      ;
+-------+--------------+------------+---------+----------+----------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+----------+------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 9.185 ns   ; state.s1 ; led1 ; key        ;
; N/A   ; None         ; 8.879 ns   ; state.s0 ; led2 ; key        ;
+-------+--------------+------------+----------+------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+---------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To       ; To Clock ;
+---------------+-------------+-----------+---------+----------+----------+
; N/A           ; None        ; 1.122 ns  ; code[0] ; temp[0]  ; key      ;
; N/A           ; None        ; 0.997 ns  ; code[2] ; temp[2]  ; key      ;
; N/A           ; None        ; 0.866 ns  ; code[1] ; temp[1]  ; key      ;
; N/A           ; None        ; 0.319 ns  ; code[0] ; state.s1 ; key      ;
; N/A           ; None        ; 0.168 ns  ; code[2] ; state.s1 ; key      ;
; N/A           ; None        ; 0.164 ns  ; change  ; state.s0 ; key      ;
; N/A           ; None        ; 0.164 ns  ; change  ; state.s2 ; key      ;
; N/A           ; None        ; 0.010 ns  ; code[1] ; state.s1 ; key      ;
; N/A           ; None        ; -0.259 ns ; code[0] ; state.s0 ; key      ;
; N/A           ; None        ; -0.410 ns ; code[2] ; state.s0 ; key      ;
; N/A           ; None        ; -0.568 ns ; code[1] ; state.s0 ; key      ;
; N/A           ; None        ; -3.295 ns ; code[6] ; temp[6]  ; key      ;
; N/A           ; None        ; -3.402 ns ; code[3] ; temp[3]  ; key      ;
; N/A           ; None        ; -3.529 ns ; code[4] ; temp[4]  ; key      ;
; N/A           ; None        ; -3.576 ns ; code[5] ; temp[5]  ; key      ;
; N/A           ; None        ; -3.631 ns ; code[7] ; temp[7]  ; key      ;
; N/A           ; None        ; -4.106 ns ; code[3] ; state.s1 ; key      ;
; N/A           ; None        ; -4.490 ns ; code[5] ; state.s1 ; key      ;
; N/A           ; None        ; -4.684 ns ; code[3] ; state.s0 ; key      ;
; N/A           ; None        ; -5.068 ns ; code[5] ; state.s0 ; key      ;
; N/A           ; None        ; -5.279 ns ; code[7] ; state.s1 ; key      ;
; N/A           ; None        ; -5.317 ns ; code[6] ; state.s1 ; key      ;
; N/A           ; None        ; -5.587 ns ; code[4] ; state.s1 ; key      ;
; N/A           ; None        ; -5.857 ns ; code[7] ; state.s0 ; key      ;
; N/A           ; None        ; -5.895 ns ; code[6] ; state.s0 ; key      ;
; N/A           ; None        ; -6.165 ns ; code[4] ; state.s0 ; key      ;
+---------------+-------------+-----------+---------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
    Info: Processing started: Wed Dec 19 13:10:27 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lock -c lcok --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "key" is an undefined clock
Info: Clock "key" has Internal fmax of 289.44 MHz between source register "temp[6]" and destination register "state.s0" (period= 3.455 ns)
    Info: + Longest register to register delay is 3.235 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y23_N9; Fanout = 1; REG Node = 'temp[6]'
        Info: 2: + IC(0.307 ns) + CELL(0.428 ns) = 0.735 ns; Loc. = LCCOMB_X16_Y23_N12; Fanout = 1; COMB Node = 'Select~75'
        Info: 3: + IC(0.923 ns) + CELL(0.153 ns) = 1.811 ns; Loc. = LCCOMB_X16_Y23_N16; Fanout = 1; COMB Node = 'Select~76'
        Info: 4: + IC(0.313 ns) + CELL(0.447 ns) = 2.571 ns; Loc. = LCCOMB_X16_Y23_N24; Fanout = 2; COMB Node = 'Select~79'
        Info: 5: + IC(0.298 ns) + CELL(0.280 ns) = 3.149 ns; Loc. = LCCOMB_X16_Y23_N18; Fanout = 1; COMB Node = 'Select~80'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 3.235 ns; Loc. = LCFF_X16_Y23_N19; Fanout = 2; REG Node = 'state.s0'
        Info: Total cell delay = 1.394 ns ( 43.09 % )
        Info: Total interconnect delay = 1.841 ns ( 56.91 % )
    Info: - Smallest clock skew is -0.001 ns
        Info: + Shortest clock path from clock "key" to destination register is 3.507 ns
            Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_G26; Fanout = 11; CLK Node = 'key'
            Info: 2: + IC(2.154 ns) + CELL(0.548 ns) = 3.507 ns; Loc. = LCFF_X16_Y23_N19; Fanout = 2; REG Node = 'state.s0'
            Info: Total cell delay = 1.353 ns ( 38.58 % )
            Info: Total interconnect delay = 2.154 ns ( 61.42 % )
        Info: - Longest clock path from clock "key" to source register is 3.508 ns
            Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_G26; Fanout = 11; CLK Node = 'key'
            Info: 2: + IC(2.155 ns) + CELL(0.548 ns) = 3.508 ns; Loc. = LCFF_X16_Y23_N9; Fanout = 1; REG Node = 'temp[6]'
            Info: Total cell delay = 1.353 ns ( 38.57 % )
            Info: Total interconnect delay = 2.155 ns ( 61.43 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "state.s0" (data pin = "code[4]", clock pin = "key") is 6.299 ns
    Info: + Longest pin to register delay is 9.842 ns
        Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_U3; Fanout = 2; PIN Node = 'code[4]'
        Info: 2: + IC(6.384 ns) + CELL(0.153 ns) = 7.342 ns; Loc. = LCCOMB_X16_Y23_N12; Fanout = 1; COMB Node = 'Select~75'
        Info: 3: + IC(0.923 ns) + CELL(0.153 ns) = 8.418 ns; Loc. = LCCOMB_X16_Y23_N16; Fanout = 1; COMB Node = 'Select~76'
        Info: 4: + IC(0.313 ns) + CELL(0.447 ns) = 9.178 ns; Loc. = LCCOMB_X16_Y23_N24; Fanout = 2; COMB Node = 'Select~79'
        Info: 5: + IC(0.298 ns) + CELL(0.280 ns) = 9.756 ns; Loc. = LCCOMB_X16_Y23_N18; Fanout = 1; COMB Node = 'Select~80'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 9.842 ns; Loc. = LCFF_X16_Y23_N19; Fanout = 2; REG Node = 'state.s0'
        Info: Total cell delay = 1.924 ns ( 19.55 % )
        Info: Total interconnect delay = 7.918 ns ( 80.45 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "key" to destination register is 3.507 ns
        Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_G26; Fanout = 11; CLK Node = 'key'
        Info: 2: + IC(2.154 ns) + CELL(0.548 ns) = 3.507 ns; Loc. = LCFF_X16_Y23_N19; Fanout = 2; REG Node = 'state.s0'
        Info: Total cell delay = 1.353 ns ( 38.58 % )
        Info: Total interconnect delay = 2.154 ns ( 61.42 % )
Info: tco from clock "key" to destination pin "led1" through register "state.s1" is 9.185 ns
    Info: + Longest clock path from clock "key" to source register is 3.507 ns
        Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_G26; Fanout = 11; CLK Node = 'key'
        Info: 2: + IC(2.154 ns) + CELL(0.548 ns) = 3.507 ns; Loc. = LCFF_X16_Y23_N25; Fanout = 3; REG Node = 'state.s1'
        Info: Total cell delay = 1.353 ns ( 38.58 % )
        Info: Total interconnect delay = 2.154 ns ( 61.42 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Longest register to pin delay is 5.423 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y23_N25; Fanout = 3; REG Node = 'state.s1'
        Info: 2: + IC(2.885 ns) + CELL(2.538 ns) = 5.423 ns; Loc. = PIN_AE23; Fanout = 0; PIN Node = 'led1'
        Info: Total cell delay = 2.538 ns ( 46.80 % )
        Info: Total interconnect delay = 2.885 ns ( 53.20 % )
Info: th for register "temp[0]" (data pin = "code[0]", clock pin = "key") is 1.122 ns
    Info: + Longest clock path from clock "key" to destination register is 3.508 ns
        Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_G26; Fanout = 11; CLK Node = 'key'
        Info: 2: + IC(2.155 ns) + CELL(0.548 ns) = 3.508 ns; Loc. = LCFF_X16_Y23_N23; Fanout = 1; REG Node = 'temp[0]'
        Info: Total cell delay = 1.353 ns ( 38.57 % )
        Info: Total interconnect delay = 2.155 ns ( 61.43 % )
    Info: + Micro hold delay of destination is 0.170 ns
    Info: - Shortest pin to register delay is 2.556 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N1; Fanout = 2; PIN Node = 'code[0]'
        Info: 2: + IC(1.372 ns) + CELL(0.153 ns) = 2.470 ns; Loc. = LCCOMB_X16_Y23_N22; Fanout = 1; COMB Node = 'temp[0]~24'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 2.556 ns; Loc. = LCFF_X16_Y23_N23; Fanout = 1; REG Node = 'temp[0]'
        Info: Total cell delay = 1.184 ns ( 46.32 % )
        Info: Total interconnect delay = 1.372 ns ( 53.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 19 13:10:28 2007
    Info: Elapsed time: 00:00:02