📄 lcok.tan.rpt
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Timing Analyzer report for lcok
Wed Dec 19 13:10:28 2007
Version 5.0 Build 148 04/26/2005 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'key'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.299 ns ; code[4] ; state.s0 ; ; key ; 0 ;
; Worst-case tco ; N/A ; None ; 9.185 ns ; state.s1 ; led1 ; key ; ; 0 ;
; Worst-case th ; N/A ; None ; 1.122 ns ; code[0] ; temp[0] ; ; key ; 0 ;
; Clock Setup: 'key' ; N/A ; None ; 289.44 MHz ( period = 3.455 ns ) ; temp[6] ; state.s0 ; key ; key ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Preliminary ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; key ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'key' ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 289.44 MHz ( period = 3.455 ns ) ; temp[6] ; state.s0 ; key ; key ; None ; None ; 3.235 ns ;
; N/A ; 327.98 MHz ( period = 3.049 ns ) ; temp[4] ; state.s0 ; key ; key ; None ; None ; 2.829 ns ;
; N/A ; 347.58 MHz ( period = 2.877 ns ) ; temp[6] ; state.s1 ; key ; key ; None ; None ; 2.657 ns ;
; N/A ; 373.69 MHz ( period = 2.676 ns ) ; temp[7] ; state.s0 ; key ; key ; None ; None ; 2.456 ns ;
; N/A ; 404.69 MHz ( period = 2.471 ns ) ; temp[4] ; state.s1 ; key ; key ; None ; None ; 2.251 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[7] ; state.s1 ; key ; key ; None ; None ; 1.878 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[2] ; state.s0 ; key ; key ; None ; None ; 1.790 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[5] ; state.s0 ; key ; key ; None ; None ; 1.753 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[1] ; state.s0 ; key ; key ; None ; None ; 1.668 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[0] ; state.s0 ; key ; key ; None ; None ; 1.637 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[3] ; state.s0 ; key ; key ; None ; None ; 1.512 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[2] ; state.s1 ; key ; key ; None ; None ; 1.212 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[5] ; state.s1 ; key ; key ; None ; None ; 1.175 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s0 ; state.s0 ; key ; key ; None ; None ; 1.126 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[1] ; state.s1 ; key ; key ; None ; None ; 1.090 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[0] ; state.s1 ; key ; key ; None ; None ; 1.059 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[4] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[6] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[7] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[0] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[3] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[2] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[1] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s2 ; temp[5] ; key ; key ; None ; None ; 0.970 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; temp[3] ; state.s1 ; key ; key ; None ; None ; 0.934 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s1 ; state.s0 ; key ; key ; None ; None ; 0.758 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s1 ; state.s2 ; key ; key ; None ; None ; 0.757 ns ;
; N/A ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; state.s0 ; state.s1 ; key ; key ; None ; None ; 0.548 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+---------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+---------+----------+----------+
; N/A ; None ; 6.299 ns ; code[4] ; state.s0 ; key ;
; N/A ; None ; 6.029 ns ; code[6] ; state.s0 ; key ;
; N/A ; None ; 5.991 ns ; code[7] ; state.s0 ; key ;
; N/A ; None ; 5.721 ns ; code[4] ; state.s1 ; key ;
; N/A ; None ; 5.451 ns ; code[6] ; state.s1 ; key ;
; N/A ; None ; 5.413 ns ; code[7] ; state.s1 ; key ;
; N/A ; None ; 5.202 ns ; code[5] ; state.s0 ; key ;
; N/A ; None ; 4.818 ns ; code[3] ; state.s0 ; key ;
; N/A ; None ; 4.624 ns ; code[5] ; state.s1 ; key ;
; N/A ; None ; 4.240 ns ; code[3] ; state.s1 ; key ;
; N/A ; None ; 3.765 ns ; code[7] ; temp[7] ; key ;
; N/A ; None ; 3.710 ns ; code[5] ; temp[5] ; key ;
; N/A ; None ; 3.663 ns ; code[4] ; temp[4] ; key ;
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