sevenseg_case.map.qmsg

sevenseg_case verilog code

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 09 19:03:19 2009 " "Info: Processing started: Thu Apr 09 19:03:19 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sevenseg_case -c sevenseg_case " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sevenseg_case -c sevenseg_case" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sevenseg_case.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sevenseg_case.v" { { "Info" "ISGN_ENTITY_NAME" "1 sevenseg_case " "Info: Found entity 1: sevenseg_case" {  } { { "sevenseg_case.v" "" { Text "C:/Documents and Settings/vlsilab/