sevenseg_case.tan.summary

sevenseg_case verilog code

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.894 ns
From           : seg[2]~reg0
To             : seg[2]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 100.05 MHz ( period = 9.995 ns )
From           : counter[22]
To             : counter[4]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'up_down'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 220.95 MHz ( period = 4.526 ns )
From           : udreg
To             : udreg
From Clock     : up_down
To Clock       : up_down
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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