sevenseg_case.map.summary

来自「sevenseg_case verilog code」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Thu Apr 09 19:03:20 2009
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : sevenseg_case
Top-level Entity Name : sevenseg_case
Family : APEX20KE
Device : EP20K200EFC484-2X
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 46
Total pins : 10
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0