📄 io_map.h
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#define PARTIDH_ID9_MASK 2
#define PARTIDH_ID10_MASK 4
#define PARTIDH_ID11_MASK 8
#define PARTIDH_ID12_MASK 16
#define PARTIDH_ID13_MASK 32
#define PARTIDH_ID14_MASK 64
#define PARTIDH_ID15_MASK 128
/*** PARTIDL - Part ID Register Low; 0x0000001B ***/
union {
byte Byte;
struct {
byte ID0 :1; /* Part ID Register Bit 0 */
byte ID1 :1; /* Part ID Register Bit 1 */
byte ID2 :1; /* Part ID Register Bit 2 */
byte ID3 :1; /* Part ID Register Bit 3 */
byte ID4 :1; /* Part ID Register Bit 4 */
byte ID5 :1; /* Part ID Register Bit 5 */
byte ID6 :1; /* Part ID Register Bit 6 */
byte ID7 :1; /* Part ID Register Bit 7 */
} Bits;
} PARTIDLSTR;
#define PARTIDL _PARTID.Overlap_STR.PARTIDLSTR.Byte
#define PARTIDL_ID0 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID0
#define PARTIDL_ID1 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID1
#define PARTIDL_ID2 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID2
#define PARTIDL_ID3 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID3
#define PARTIDL_ID4 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID4
#define PARTIDL_ID5 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID5
#define PARTIDL_ID6 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID6
#define PARTIDL_ID7 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID7
#define PARTIDL_ID0_MASK 1
#define PARTIDL_ID1_MASK 2
#define PARTIDL_ID2_MASK 4
#define PARTIDL_ID3_MASK 8
#define PARTIDL_ID4_MASK 16
#define PARTIDL_ID5_MASK 32
#define PARTIDL_ID6_MASK 64
#define PARTIDL_ID7_MASK 128
} Overlap_STR;
struct {
word ID0 :1; /* Part ID Register Bit 0 */
word ID1 :1; /* Part ID Register Bit 1 */
word ID2 :1; /* Part ID Register Bit 2 */
word ID3 :1; /* Part ID Register Bit 3 */
word ID4 :1; /* Part ID Register Bit 4 */
word ID5 :1; /* Part ID Register Bit 5 */
word ID6 :1; /* Part ID Register Bit 6 */
word ID7 :1; /* Part ID Register Bit 7 */
word ID8 :1; /* Part ID Register Bit 8 */
word ID9 :1; /* Part ID Register Bit 9 */
word ID10 :1; /* Part ID Register Bit 10 */
word ID11 :1; /* Part ID Register Bit 11 */
word ID12 :1; /* Part ID Register Bit 12 */
word ID13 :1; /* Part ID Register Bit 13 */
word ID14 :1; /* Part ID Register Bit 14 */
word ID15 :1; /* Part ID Register Bit 15 */
} Bits;
} PARTIDSTR;
extern volatile PARTIDSTR _PARTID @(REG_BASE + 0x0000001A);
#define PARTID _PARTID.Word
#define PARTID_ID0 _PARTID.Bits.ID0
#define PARTID_ID1 _PARTID.Bits.ID1
#define PARTID_ID2 _PARTID.Bits.ID2
#define PARTID_ID3 _PARTID.Bits.ID3
#define PARTID_ID4 _PARTID.Bits.ID4
#define PARTID_ID5 _PARTID.Bits.ID5
#define PARTID_ID6 _PARTID.Bits.ID6
#define PARTID_ID7 _PARTID.Bits.ID7
#define PARTID_ID8 _PARTID.Bits.ID8
#define PARTID_ID9 _PARTID.Bits.ID9
#define PARTID_ID10 _PARTID.Bits.ID10
#define PARTID_ID11 _PARTID.Bits.ID11
#define PARTID_ID12 _PARTID.Bits.ID12
#define PARTID_ID13 _PARTID.Bits.ID13
#define PARTID_ID14 _PARTID.Bits.ID14
#define PARTID_ID15 _PARTID.Bits.ID15
#define PARTID_ID0_MASK 1
#define PARTID_ID1_MASK 2
#define PARTID_ID2_MASK 4
#define PARTID_ID3_MASK 8
#define PARTID_ID4_MASK 16
#define PARTID_ID5_MASK 32
#define PARTID_ID6_MASK 64
#define PARTID_ID7_MASK 128
#define PARTID_ID8_MASK 256
#define PARTID_ID9_MASK 512
#define PARTID_ID10_MASK 1024
#define PARTID_ID11_MASK 2048
#define PARTID_ID12_MASK 4096
#define PARTID_ID13_MASK 8192
#define PARTID_ID14_MASK 16384
#define PARTID_ID15_MASK 32768
/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
typedef union {
byte Byte;
struct {
byte ram_sw0 :1; /* Allocated System RAM Memory Space Bit 0 */
byte ram_sw1 :1; /* Allocated System RAM Memory Space Bit 1 */
byte ram_sw2 :1; /* Allocated System RAM Memory Space Bit 2 */
byte :1;
byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */
byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */
byte :1;
byte reg_sw0 :1; /* Allocated System Register Space */
} Bits;
struct {
byte grpram_sw :3;
byte :1;
byte grpeep_sw :2;
byte :1;
byte grpreg_sw :1;
} MergedBits;
} MEMSIZ0STR;
extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
#define MEMSIZ0 _MEMSIZ0.Byte
#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
/* MEMSIZ_ARR: Access 2 MEMSIZx registers in an array */
#define MEMSIZ_ARR ((volatile byte *) &MEMSIZ0)
#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw
#define MEMSIZ0_ram_sw0_MASK 1
#define MEMSIZ0_ram_sw1_MASK 2
#define MEMSIZ0_ram_sw2_MASK 4
#define MEMSIZ0_eep_sw0_MASK 16
#define MEMSIZ0_eep_sw1_MASK 32
#define MEMSIZ0_reg_sw0_MASK 128
#define MEMSIZ0_ram_sw_MASK 7
#define MEMSIZ0_ram_sw_BITNUM 0
#define MEMSIZ0_eep_sw_MASK 48
#define MEMSIZ0_eep_sw_BITNUM 4
/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
typedef union {
byte Byte;
struct {
byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */
byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */
byte :1;
byte :1;
byte :1;
byte :1;
byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
} Bits;
struct {
byte grppag_sw :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte grprom_sw :2;
} MergedBits;
} MEMSIZ1STR;
extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
#define MEMSIZ1 _MEMSIZ1.Byte
#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw
#define MEMSIZ1_pag_sw0_MASK 1
#define MEMSIZ1_pag_sw1_MASK 2
#define MEMSIZ1_rom_sw0_MASK 64
#define MEMSIZ1_rom_sw1_MASK 128
#define MEMSIZ1_pag_sw_MASK 3
#define MEMSIZ1_pag_sw_BITNUM 0
#define MEMSIZ1_rom_sw_MASK 192
#define MEMSIZ1_rom_sw_BITNUM 6
/*** INTCR - Interrupt Control Register; 0x0000001E ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte IRQEN :1; /* External IRQ Enable */
byte IRQE :1; /* IRQ Select Edge Sensitive Only */
} Bits;
} INTCRSTR;
extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
#define INTCR _INTCR.Byte
#define INTCR_IRQEN _INTCR.Bits.IRQEN
#define INTCR_IRQE _INTCR.Bits.IRQE
#define INTCR_IRQEN_MASK 64
#define INTCR_IRQE_MASK 128
/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
typedef union {
byte Byte;
struct {
byte :1;
byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */
byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */
byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */
byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */
byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */
byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */
byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */
} Bits;
struct {
byte :1;
byte grpPSEL_1 :7;
} MergedBits;
} HPRIOSTR;
extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
#define HPRIO _HPRIO.Byte
#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
#define HPRIO_PSEL HPRIO_PSEL_1
#define HPRIO_PSEL1_MASK 2
#define HPRIO_PSEL2_MASK 4
#define HPRIO_PSEL3_MASK 8
#define HPRIO_PSEL4_MASK 16
#define HPRIO_PSEL5_MASK 32
#define HPRIO_PSEL6_MASK 64
#define HPRIO_PSEL7_MASK 128
#define HPRIO_PSEL_1_MASK 254
#define HPRIO_PSEL_1_BITNUM 1
/*** DBGC1 - Debug Control Register 1; 0x00000020 ***/
typedef union {
byte Byte;
struct {
byte CAPMOD0 :1; /* Capture Mode Field, bit 0 */
byte CAPMOD1 :1; /* Capture Mode Field, bit 1 */
byte :1;
byte DBGBRK :1; /* DBG Breakpoint Enable Bit */
byte BEGIN :1; /* Begin/End Trigger Bit */
byte TRGSEL :1; /* Trigger Selection Bit */
byte ARM :1; /* Arm Bit */
byte DBGEN :1; /* DBG Mode Enable Bit */
} Bits;
struct {
byte grpCAPMOD :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} DBGC1STR;
extern volatile DBGC1STR _DBGC1 @(REG_BASE + 0x00000020);
#define DBGC1 _DBGC1.Byte
#define DBGC1_CAPMOD0 _DBGC1.Bits.CAPMOD0
#define DBGC1_CAPMOD1 _DBGC1.Bits.CAPMOD1
#define DBGC1_DBGBRK _DBGC1.Bits.DBGBRK
#define DBGC1_BEGIN _DBGC1.Bits.BEGIN
#define DBGC1_TRGSEL _DBGC1.Bits.TRGSEL
#define DBGC1_ARM _DBGC1.Bits.ARM
#define DBGC1_DBGEN _DBGC1.Bits.DBGEN
#define DBGC1_CAPMOD _DBGC1.MergedBits.grpCAPMOD
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