📄 io_map.h
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/** ###################################################################
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
** Filename : IO_Map.H
** Project : eeprom
** Processor : MC9S12HZ64CFU
** Beantype : IO_Map
** Version : Driver 01.06
** Compiler : CodeWarrior HC12 C Compiler
** Date/Time : 2008-12-15, 上午 10:41
** Abstract :
** IO_Map.h - implements an IO device's mapping.
** This module contains symbol definitions of all peripheral
** registers and bits.
** Settings :
**
** Contents :
** No public methods
**
** (c) Copyright UNIS, spol. s r.o. 1997-2007
** UNIS, spol. s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
** http : www.processorexpert.com
** mail : info@processorexpert.com
** ###################################################################*/
#ifndef _IO_MAP_H
#define _IO_MAP_H
/* Linker pragmas */
#pragma LINK_INFO DERIVATIVE "MC9S12HZ64"
#pragma LINK_INFO OSCFREQUENCY "16000000"
#define REG_BASE 0x0000 /* Base address for the I/O register block */
/* Based on CPU DB MC9S12HZ64_80, version 2.87.443 (RegistersPrg V2.20) */
/* DataSheet : MC9S12HZ256 Rev. 2.01 10/2005 */
#include "PE_Types.h"
#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
#pragma OPTION ADD V30toV31Compatible "-BfaGapLimitBits4294967295" /*this guarantee correct bitfield positions*/
/*********************************************/
/* */
/* PE I/O map */
/* */
/*********************************************/
/**************** interrupt vector numbers ****************/
#define VectorNumber_VReserved63 63
#define VectorNumber_VReserved62 62
#define VectorNumber_VReserved61 61
#define VectorNumber_VReserved60 60
#define VectorNumber_VReserved59 59
#define VectorNumber_Vvreglvi 58
#define VectorNumber_Vpwmesdn 57
#define VectorNumber_VReserved56 56
#define VectorNumber_VReserved55 55
#define VectorNumber_VReserved54 54
#define VectorNumber_VReserved53 53
#define VectorNumber_Vmctimovf 52
#define VectorNumber_VReserved51 51
#define VectorNumber_VReserved50 50
#define VectorNumber_VReserved49 49
#define VectorNumber_Vssd1 48
#define VectorNumber_Vssd0 47
#define VectorNumber_VReserved46 46
#define VectorNumber_VReserved45 45
#define VectorNumber_VReserved44 44
#define VectorNumber_VReserved43 43
#define VectorNumber_VReserved42 42
#define VectorNumber_VReserved41 41
#define VectorNumber_VReserved40 40
#define VectorNumber_Vcan0tx 39
#define VectorNumber_Vcan0rx 38
#define VectorNumber_Vcan0err 37
#define VectorNumber_Vcan0wkup 36
#define VectorNumber_Vflash 35
#define VectorNumber_Veeprom 34
#define VectorNumber_VReserved33 33
#define VectorNumber_VReserved32 32
#define VectorNumber_VReserved31 31
#define VectorNumber_VReserved30 30
#define VectorNumber_Vcrgscm 29
#define VectorNumber_Vcrgplllck 28
#define VectorNumber_Vportad 27
#define VectorNumber_VReserved26 26
#define VectorNumber_VReserved25 25
#define VectorNumber_VReserved24 24
#define VectorNumber_VReserved23 23
#define VectorNumber_Vatd 22
#define VectorNumber_VReserved21 21
#define VectorNumber_Vsci0 20
#define VectorNumber_VReserved19 19
#define VectorNumber_Vtimpaie 18
#define VectorNumber_Vtimpaovf 17
#define VectorNumber_Vtimovf 16
#define VectorNumber_Vtimch7 15
#define VectorNumber_Vtimch6 14
#define VectorNumber_Vtimch5 13
#define VectorNumber_Vtimch4 12
#define VectorNumber_Vtimch3 11
#define VectorNumber_Vtimch2 10
#define VectorNumber_Vtimch1 9
#define VectorNumber_Vtimch0 8
#define VectorNumber_Vrti 7
#define VectorNumber_VReserved6 6
#define VectorNumber_Vxirq 5
#define VectorNumber_Vswi 4
#define VectorNumber_Vtrap 3
#define VectorNumber_Vcop 2
#define VectorNumber_Vclkmon 1
#define VectorNumber_Vreset 0
/**************** interrupt vector table ****************/
#define VReserved63 0x0000FF80
#define VReserved62 0x0000FF82
#define VReserved61 0x0000FF84
#define VReserved60 0x0000FF86
#define VReserved59 0x0000FF88
#define Vvreglvi 0x0000FF8A
#define Vpwmesdn 0x0000FF8C
#define VReserved56 0x0000FF8E
#define VReserved55 0x0000FF90
#define VReserved54 0x0000FF92
#define VReserved53 0x0000FF94
#define Vmctimovf 0x0000FF96
#define VReserved51 0x0000FF98
#define VReserved50 0x0000FF9A
#define VReserved49 0x0000FF9C
#define Vssd1 0x0000FF9E
#define Vssd0 0x0000FFA0
#define VReserved46 0x0000FFA2
#define VReserved45 0x0000FFA4
#define VReserved44 0x0000FFA6
#define VReserved43 0x0000FFA8
#define VReserved42 0x0000FFAA
#define VReserved41 0x0000FFAC
#define VReserved40 0x0000FFAE
#define Vcan0tx 0x0000FFB0
#define Vcan0rx 0x0000FFB2
#define Vcan0err 0x0000FFB4
#define Vcan0wkup 0x0000FFB6
#define Vflash 0x0000FFB8
#define Veeprom 0x0000FFBA
#define VReserved33 0x0000FFBC
#define VReserved32 0x0000FFBE
#define VReserved31 0x0000FFC0
#define VReserved30 0x0000FFC2
#define Vcrgscm 0x0000FFC4
#define Vcrgplllck 0x0000FFC6
#define Vportad 0x0000FFC8
#define VReserved26 0x0000FFCA
#define VReserved25 0x0000FFCC
#define VReserved24 0x0000FFCE
#define VReserved23 0x0000FFD0
#define Vatd 0x0000FFD2
#define VReserved21 0x0000FFD4
#define Vsci0 0x0000FFD6
#define VReserved19 0x0000FFD8
#define Vtimpaie 0x0000FFDA
#define Vtimpaovf 0x0000FFDC
#define Vtimovf 0x0000FFDE
#define Vtimch7 0x0000FFE0
#define Vtimch6 0x0000FFE2
#define Vtimch5 0x0000FFE4
#define Vtimch4 0x0000FFE6
#define Vtimch3 0x0000FFE8
#define Vtimch2 0x0000FFEA
#define Vtimch1 0x0000FFEC
#define Vtimch0 0x0000FFEE
#define Vrti 0x0000FFF0
#define VReserved6 0x0000FFF2
#define Vxirq 0x0000FFF4
#define Vswi 0x0000FFF6
#define Vtrap 0x0000FFF8
#define Vcop 0x0000FFFA
#define Vclkmon 0x0000FFFC
#define Vreset 0x0000FFFE
/**************** registers I/O map ****************/
/*** PORTA - Port A Register; 0x00000000 ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* Port A Bit 0 */
byte BIT1 :1; /* Port A Bit 1 */
byte BIT2 :1; /* Port A Bit 2 */
byte BIT3 :1; /* Port A Bit 3 */
byte BIT4 :1; /* Port A Bit 4 */
byte BIT5 :1; /* Port A Bit 5 */
byte BIT6 :1; /* Port A Bit 6 */
byte BIT7 :1; /* Port A Bit 7 */
} Bits;
} PORTASTR;
extern volatile PORTASTR _PORTA @(REG_BASE + 0x00000000);
#define PORTA _PORTA.Byte
#define PORTA_BIT0 _PORTA.Bits.BIT0
#define PORTA_BIT1 _PORTA.Bits.BIT1
#define PORTA_BIT2 _PORTA.Bits.BIT2
#define PORTA_BIT3 _PORTA.Bits.BIT3
#define PORTA_BIT4 _PORTA.Bits.BIT4
#define PORTA_BIT5 _PORTA.Bits.BIT5
#define PORTA_BIT6 _PORTA.Bits.BIT6
#define PORTA_BIT7 _PORTA.Bits.BIT7
#define PORTA_BIT0_MASK 1
#define PORTA_BIT1_MASK 2
#define PORTA_BIT2_MASK 4
#define PORTA_BIT3_MASK 8
#define PORTA_BIT4_MASK 16
#define PORTA_BIT5_MASK 32
#define PORTA_BIT6_MASK 64
#define PORTA_BIT7_MASK 128
/*** PORTB - Port B Register; 0x00000001 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte BIT4 :1; /* Port B Bit 4 */
byte BIT5 :1; /* Port B Bit 5 */
byte BIT6 :1; /* Port B Bit 6 */
byte BIT7 :1; /* Port B Bit 7 */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte grpBIT_4 :4;
} MergedBits;
} PORTBSTR;
extern volatile PORTBSTR _PORTB @(REG_BASE + 0x00000001);
#define PORTB _PORTB.Byte
#define PORTB_BIT4 _PORTB.Bits.BIT4
#define PORTB_BIT5 _PORTB.Bits.BIT5
#define PORTB_BIT6 _PORTB.Bits.BIT6
#define PORTB_BIT7 _PORTB.Bits.BIT7
#define PORTB_BIT_4 _PORTB.MergedBits.grpBIT_4
#define PORTB_BIT PORTB_BIT_4
#define PORTB_BIT4_MASK 16
#define PORTB_BIT5_MASK 32
#define PORTB_BIT6_MASK 64
#define PORTB_BIT7_MASK 128
#define PORTB_BIT_4_MASK 240
#define PORTB_BIT_4_BITNUM 4
/*** DDRA - Port A Data Direction Register; 0x00000002 ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* Data Direction Port A Bit 0 */
byte BIT1 :1; /* Data Direction Port A Bit 1 */
byte BIT2 :1; /* Data Direction Port A Bit 2 */
byte BIT3 :1; /* Data Direction Port A Bit 3 */
byte BIT4 :1; /* Data Direction Port A Bit 4 */
byte BIT5 :1; /* Data Direction Port A Bit 5 */
byte BIT6 :1; /* Data Direction Port A Bit 6 */
byte BIT7 :1; /* Data Direction Port A Bit 7 */
} Bits;
} DDRASTR;
extern volatile DDRASTR _DDRA @(REG_BASE + 0x00000002);
#define DDRA _DDRA.Byte
#define DDRA_BIT0 _DDRA.Bits.BIT0
#define DDRA_BIT1 _DDRA.Bits.BIT1
#define DDRA_BIT2 _DDRA.Bits.BIT2
#define DDRA_BIT3 _DDRA.Bits.BIT3
#define DDRA_BIT4 _DDRA.Bits.BIT4
#define DDRA_BIT5 _DDRA.Bits.BIT5
#define DDRA_BIT6 _DDRA.Bits.BIT6
#define DDRA_BIT7 _DDRA.Bits.BIT7
#define DDRA_BIT0_MASK 1
#define DDRA_BIT1_MASK 2
#define DDRA_BIT2_MASK 4
#define DDRA_BIT3_MASK 8
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