c8051f320_defs.h

单片机上网所使用的精简协议栈

//-----------------------------------------------------------------------------
// C8051F320_defs.h
//-----------------------------------------------------------------------------
// Copyright 2007, Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Register/bit definitions for the C8051F32x family.
// **Important Note**: The compiler_defs.h header file should be included
// before including this header file.
//
// Target:         C8051F320, 'F321
// Tool chain:     Generic
// Command Line:   None
//
// Release 2.4 - 07 AUG 2007 (PKC)
//    -Removed #include <compiler_defs.h>. The C source file should include it.
//    -Removed FID and fixed formatting.
// Release 2.3 - 29 SEP 2006 (BW)
//    -Added SFR16 defs
// Release 2.2 - 29 SEP 2006 (PKC)
//    -Reformatted header file to enable portable SFR definitions
// Release 2.1 - 09 DEC 2005 (GRP)
//    -Added EMI0CN
// Release 2.0 - 09 NOV 2005 (PKC)
//    -Converted file to new coding guidelines
//    -Added #defines for interrupt priorities
//    -Added #ifndef/#define to allow multiple includes of file
// Release 1.5
//    -Latest release before new firmware coding standard

//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------

#ifndef C8051F320_DEFS_H
#define C8051F320_DEFS_H

//-----------------------------------------------------------------------------
// Byte Registers
//-----------------------------------------------------------------------------

SFR (P0, 0x80);                        // Port0
SFR (SP, 0x81);                        // Stack pointer
SFR (DPL, 0x82);                       // Data pointer - Low byte
SFR (DPH, 0x83);                       // Data pointer - High byte
SFR (PCON, 0x87);                      // Power control register
SFR (TCON, 0x88);                      // Timer control register
SFR (TMOD, 0x89);                      // Timer mode register
SFR (TL0, 0x8A);                       // Timer0 - Low byte
SFR (TL1, 0x8B);                       // Timer1 - Low byte
SFR (TH0, 0x8C);                       // Timer0 - High byte
SFR (TH1, 0x8D);                       // Timer1 - High byte
SFR (CKCON, 0x8E);                     // Clock control register
SFR (PSCTL, 0x8F);                     // Program store r/w control
SFR (P1, 0x90);                        // Port1
SFR (TMR3CN, 0x91);                    // Timer3 control register
SFR (TMR3RLL, 0x92);                   // Timer3 reload register - Low byte
SFR (TMR3RLH, 0x93);                   // Timer3 reload register - High byte
SFR (TMR3L, 0x94);                     // Timer3 - Low byte
SFR (TMR3H, 0x95);                     // Timer3 - High byte
SFR (USB0ADR, 0x96);                   // USB0 address port
SFR (USB0DAT, 0x97);                   // USB0 data port
SFR (SCON0, 0x98);                     // UART0 control register
SFR (SBUF0, 0x99);                     // UART0 data buffer register
SFR (CPT1CN, 0x9A);                    // Comparator1 control register
SFR (CPT0CN, 0x9B);                    // Comparator0 control register
SFR (CPT1MD, 0x9C);                    // Comparator1 mode selection register
SFR (CPT0MD, 0x9D);                    // Comparator0 mode selection register
SFR (CPT1MX, 0x9E);                    // Comparator1 mux selection register
SFR (CPT0MX, 0x9F);                    // Comparator0 mux selection register
SFR (P2, 0xA0);                        // Port2
SFR (SPICFG, 0xA1);                    // SPI0 configuration register
SFR (SPI0CFG, 0xA1);                   // SPI0 configuration register
SFR (SPICKR, 0xA2);                    // SPI0 clock configuration register
SFR (SPI0CKR, 0xA2);                   // SPI0 clock configuration register
SFR (SPIDAT, 0xA3);                    // SPI0 data register
SFR (SPI0DAT, 0xA3);                   // SPI0 data register
SFR (P0MDOUT, 0xA4);                   // Port0 output mode register
SFR (P1MDOUT, 0xA5);                   // Port1 output mode register
SFR (P2MDOUT, 0xA6);                   // Port2 output mode register
SFR (P3MDOUT, 0xA7);                   // Port3 output mode register
SFR (IE, 0xA8);                        // Interrupt enable
SFR (CLKSEL, 0xA9);                    // Clock source select
SFR (EMI0CN, 0xAA);                    // External Memory Interface Control
SFR (P3, 0xB0);                        // Port3
SFR (OSCXCN, 0xB1);                    // External oscillator control
SFR (OSCICN, 0xB2);                    // Internal oscillator control
SFR (OSCICL, 0xB3);                    // Internal oscillator calibration
SFR (FLSCL, 0xB6);                     // Flash scale register
SFR (FLKEY, 0xB7);                     // Flash lock & key register
SFR (IP, 0xB8);                        // Interrupt priority
SFR (CLKMUL, 0xB9);                    // Clock multiplier control register
SFR (AMX0N, 0xBA);                     // ADC0 mux negative channel selection
SFR (AMX0P, 0xBB);                     // ADC0 mux positive channel selection
SFR (ADC0CF, 0xBC);                    // ADC0 configuration
SFR (ADC0L, 0xBD);                     // ADC0 data low
SFR (ADC0H, 0xBE);                     // ADC0 data high
SFR (SMB0CN, 0xC0);                    // SMBus control
SFR (SMB0CF, 0xC1);                    // SMBus configuration
SFR (SMB0DAT, 0xC2);                   // SMBus data
SFR (ADC0GTL, 0xC3);                   // ADC0 greater-than data low register
SFR (ADC0GTH, 0xC4);                   // ADC0 greater-than data high register
SFR (ADC0LTL, 0xC5);                   // ADC0 less-than data low register
SFR (ADC0LTH, 0xC6);                   // ADC0 less-than data high register
SFR (TMR2CN, 0xC8);                    // Timer2 control register
SFR (REG0CN, 0xC9);                    // Regulator control register
SFR (TMR2RLL, 0xCA);                   // Timer2 reload register - Low byte
SFR (TMR2RLH, 0xCB);                   // Timer2 reload register - High byte
SFR (TMR2L, 0xCC);                     // Timer2 - Low byte
SFR (TMR2H, 0xCD);                     // Timer2 - High byte
SFR (PSW, 0xD0);                       // Program Status Word
SFR (REF0CN, 0xD1);                    // Voltage reference control register
SFR (P0SKIP, 0xD4);                    // Port0 crossbar skip register
SFR (P1SKIP, 0xD5);                    // Port1 crossbar skip register
SFR (P2SKIP, 0xD6);                    // Port2 crossbar skip register
SFR (USB0XCN, 0xD7);                   // USB0 tranceiver control register
SFR (PCA0CN, 0xD8);                    // PCA0 control register
SFR (PCA0MD, 0xD9);                    // PCA0 mode register
SFR (PCA0CPM0, 0xDA);                  // Capture/compare module0 mode
SFR (PCA0CPM1, 0xDB);                  // Capture/compare module1 mode
SFR (PCA0CPM2, 0xDC);                  // Capture/compare module2 mode
SFR (PCA0CPM3, 0xDD);                  // Capture/compare module3 mode
SFR (PCA0CPM4, 0xDE);                  // Capture/compare module4 mode
SFR (ACC, 0xE0);                       // Accumulator
SFR (XBR0, 0xE1);                      // Port I/O crossbar register 0
SFR (XBR1, 0xE2);                      // Port I/O crossbar register 1
SFR (IT01CF, 0xE4);                    // Int0/int1 configuration register
SFR (EIE1, 0xE6);                      // Extended interrupt enable 1
SFR (EIE2, 0xE7);                      // Extended interrupt enable 2
SFR (ADC0CN, 0xE8);                    // ADC0 control register
SFR (PCA0CPL1, 0xE9);                  // Capture/compare module1 - Low byte
SFR (PCA0CPH1, 0xEA);                  // Capture/compare module1 - High byte
SFR (PCA0CPL2, 0xEB);                  // Capture/compare module2 - Low byte
SFR (PCA0CPH2, 0xEC);                  // Capture/compare module2 - High byte
SFR (PCA0CPL3, 0xED);                  // Capture/compare module3 - Low byte
SFR (PCA0CPH3, 0xEE);                  // Capture/compare module3 - High byte
SFR (RSTSRC, 0xEF);                    // Reset source register
SFR (B, 0xF0);                         // B register
SFR (P0MDIN, 0xF1);                    // Port0 input mode register
SFR (P1MDIN, 0xF2);                    // Port1 input mode register
SFR (P2MDIN, 0xF3);                    // Port2 input mode register
SFR (P3MDIN, 0xF4);                    // Port3 input mode register
SFR (EIP1, 0xF6);                      // Extended interrupt priority 1
SFR (EIP2, 0xF7);                      // Extended interrupt priority 2
SFR (SPI0CN, 0xF8);                    // SPI0 control register
SFR (PCA0L, 0xF9);                     // PCA0 counter/timer - Low byte
SFR (PCA0H, 0xFA);                     // PCA0 counter/timer - High byte
SFR (PCA0CPL0, 0xFB);                  // Capture/compare module0 - Low byte
SFR (PCA0CPH0, 0xFC);                  // Capture/compare module0 - High byte
SFR (PCA0CPL4, 0xFD);                  // Capture/compare module4 - Low byte
SFR (PCA0CPH4, 0xFE);                  // Capture/compare module4 - High byte
SFR (VDM0CN, 0xFF);                    // Vdd monitor control

//-----------------------------------------------------------------------------
// 16-bit Register Definitions (might not be supported by all compilers)
//-----------------------------------------------------------------------------

SFR16 (DP, 0x82);
SFR16 (TMR3RL, 0x92);
SFR16 (TMR3, 0x94);
SFR16 (ADC0, 0xBD);
SFR16 (ADC0GT, 0xC3);
SFR16 (ADC0LT, 0xC5);
SFR16 (TMR2RL, 0xCA);