📄 tms320f2812寄存器详细定义.txt
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/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*该文件是定义寄存器地址的头文件：F2812REGS_C.H*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#ifndef F2812REGS_C_H
#define F2812REGS_C_H
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定义CPU中断标志寄存器和中断屏蔽寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
extern cregister volatile UWORD IER;
extern cregister volatile UWORD IFR;
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定义装置仿真寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define DEVICECNF ((REGS16U)0x000880) /* Device Configuration Register */
#define DEVICEID ((REGS16U)0x000882) /* Device ID Register */
#define PROTSTART ((REGS16U)0x000884) /* Block Protection Start Address Register */
#define PROTRANGE ((REGS16U)0x000885) /* Block Protection Range Address Register */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定义FLASH和OTP配置寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define FOPT ((REGS16U)0x000A80) /* Flash Option Register */
#define FPWR ((REGS16U)0x000A82) /* Flash Power Modes Register */
#define FSTATUS ((REGS16U)0x000A83) /* Status Register */
#define FSTDBYWAIT ((REGS16U)0x000A84) /* Flash Sleep To Standby Wait State Register */
#define FACTIVEWAIT ((REGS16U)0x000A85) /* Flash Standby To Active Wait State Register */
#define FBANKWAIT ((REGS16U)0x000A86) /* Flash Read Access Wait State Register */
#define FOTPWAIT ((REGS16U)0x000A87) /* OTP Read Access Wait State Register */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定义CSM寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define KEY0 ((REGS16U)0x000AE0) /* Low word of the 128-bit KEY register */
#define KEY1 ((REGS16U)0x000AE1) /* Next word of the 128-bit KEY register */
#define KEY2 ((REGS16U)0x000AE2) /* Next word of the 128-bit KEY register */
#define KEY3 ((REGS16U)0x000AE3) /* Next word of the 128-bit KEY register */
#define KEY4 ((REGS16U)0x000AE4) /* Next word of the 128-bit KEY register */
#define KEY5 ((REGS16U)0x000AE5) /* Next word of the 128-bit KEY register */
#define KEY6 ((REGS16U)0x000AE6) /* Next word of the 128-bit KEY register */
#define KEY7 ((REGS16U)0x000AE7) /* High word of the 128-bit KEY register */
#define CSMSCR ((REGS16U)0x000AEF) /* CSM status and control register */
#define PWL0 ((REGS16U)0x3F7FF8) /* Low word of the 128-bit password */
#define PWL1 ((REGS16U)0x3F7FF9) /* Next word of the 128-bit password */
#define PWL2 ((REGS16U)0x3F7FFA) /* Next word of the 128-bit password */
#define PWL3 ((REGS16U)0x3F7FFB) /* Next word of the 128-bit password */
#define PWL4 ((REGS16U)0x3F7FFC) /* Next word of the 128-bit password */
#define PWL5 ((REGS16U)0x3F7FFD) /* Next word of the 128-bit password */
#define PWL6 ((REGS16U)0x3F7FFE) /* Next word of the 128-bit password */
#define PWL7 ((REGS16U)0x3F7FFF) /* High word of the 128-bit password */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*外部扩展端口配置与控制寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define XTIMING0 ((REGS32U)0x000B20) /* XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register */
#define XTIMING1 ((REGS32U)0x000B22) /* XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register */
#define XTIMING2 ((REGS32U)0x000B24) /* XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register */
#define XTIMING6 ((REGS32U)0x000B2C) /* XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register */
#define XTIMING7 ((REGS32U)0x000B2E) /* XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register */
#define XINTCNF2 ((REGS32U)0x000B34) /* XINTF Configuration Register can access as two 16-bit registers or one 32-bit register */
#define XBANK ((REGS16U)0x000B38) /* XINTF Bank Control Register */
#define XREVISION ((REGS16U)0x000B3A) /* XINTF Revision Register */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定义CPU定时器0、1、2的寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define TIMER0TIM ((REGS16U)0x000C00) /* CPU-Timer 0, Counter Register */
#define TIMER0TIMH ((REGS16U)0x000C01) /* CPU-Timer 0, Counter Register High */
#define TIMER0PRD ((REGS16U)0x000C02) /* CPU-Timer 0, Period Register */
#define TIMER0PRDH ((REGS16U)0x000C03) /* CPU-Timer 0, Period Register High */
#define TIMER0TCR ((REGS16U)0x000C04) /* CPU-Timer 0, Control Register */
#define TIMER0TPR ((REGS16U)0x000C06) /* CPU-Timer 0, Prescale Register */
#define TIMER0TPRH ((REGS16U)0x000C07) /* CPU-Timer 0, Prescale Register High */
#define TIMER1TIM ((REGS16U)0x000C08) /* CPU-Timer 1, Counter Register */
#define TIMER1TIMH ((REGS16U)0x000C09) /* CPU-Timer 1, Counter Register High */
#define TIMER1PRD ((REGS16U)0x000C0A) /* CPU-Timer 1, Period Register */
#define TIMER1PRDH ((REGS16U)0x000C0B) /* CPU-Timer 1, Period Register High */
#define TIMER1TCR ((REGS16U)0x000C0C) /* CPU-Timer 1, Control Register */
#define TIMER1TPR ((REGS16U)0x000C0E) /* CPU-Timer 1, Prescale Register */
#define TIMER1TPRH ((REGS16U)0x000C0F) /* CPU-Timer 1, Prescale Register High */
#define TIMER2TIM ((REGS16U)0x000C10) /* CPU-Timer 2, Counter Register */
#define TIMER2TIMH ((REGS16U)0x000C11) /* CPU-Timer 2, Counter Register High */
#define TIMER2PRD ((REGS16U)0x000C12) /* CPU-Timer 2, Period Register */
#define TIMER2PRDH ((REGS16U)0x000C13) /* CPU-Timer 2, Period Register High */
#define TIMER2TCR ((REGS16U)0x000C14) /* CPU-Timer 2, Control Register */
#define TIMER2TPR ((REGS16U)0x000C16) /* CPU-Timer 2, Prescale Register */
#define TIMER2TPRH ((REGS16U)0x000C17) /* CPU-Timer 2, Prescale Register High */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定义PIE配置与控制寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define PIECTRL ((REGS16U)0x000CE0) /* PIE, Control Register */
#define PIEACK ((REGS16U)0x000CE1) /* PIE, Acknowledge Register */
#define PIEIER1 ((REGS16U)0x000CE2) /* PIE, INT1 Group Enable Register */
#define PIEIFR1 ((REGS16U)0x000CE3) /* PIE, INT1 Group Flag Register */
#define PIEIER2 ((REGS16U)0x000CE4) /* PIE, INT2 Group Enable Register */
#define PIEIFR2 ((REGS16U)0x000CE5) /* PIE, INT2 Group Flag Register */
#define PIEIER3 ((REGS16U)0x000CE6) /* PIE, INT3 Group Enable Register */
#define PIEIFR3 ((REGS16U)0x000CE7) /* PIE, INT3 Group Flag Register */
#define PIEIER4 ((REGS16U)0x000CE8) /* PIE, INT4 Group Enable Register */
#define PIEIFR4 ((REGS16U)0x000CE9) /* PIE, INT4 Group Flag Register */
#define PIEIER5 ((REGS16U)0x000CEA) /* PIE, INT5 Group Enable Register */
#define PIEIFR5 ((REGS16U)0x000CEB) /* PIE, INT5 Group Flag Register */
#define PIEIER6 ((REGS16U)0x000CEC) /* PIE, INT6 Group Enable Register */
#define PIEIFR6 ((REGS16U)0x000CED) /* PIE, INT6 Group Flag Register */
#define PIEIER7 ((REGS16U)0x000CEE) /* PIE, INT7 Group Enable Register */
#define PIEIFR7 ((REGS16U)0x000CEF) /* PIE, INT7 Group Flag Register */
#define PIEIER8 ((REGS16U)0x000CF0) /* PIE, INT8 Group Enable Register */
#define PIEIFR8 ((REGS16U)0x000CF1) /* PIE, INT8 Group Flag Register */
#define PIEIER9 ((REGS16U)0x000CF2) /* PIE, INT9 Group Enable Register */
#define PIEIFR9 ((REGS16U)0x000CF3) /* PIE, INT9 Group Flag Register */
#define PIEIER10 ((REGS16U)0x000CF4) /* PIE, INT10 Group Enable Register */
#define PIEIFR10 ((REGS16U)0x000CF5) /* PIE, INT10 Group Flag Register */
#define PIEIER11 ((REGS16U)0x000CF6) /* PIE, INT11 Group Enable Register */
#define PIEIFR11 ((REGS16U)0x000CF7) /* PIE, INT11 Group Flag Register */
#define PIEIER12 ((REGS16U)0x000CF8) /* PIE, INT12 Group Enable Register */
#define PIEIFR12 ((REGS16U)0x000CF9) /* PIE, INT12 Group Flag Register */
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/*定义CAN模块寄存器*/
/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* CAN模块控制寄存器 */
#define CANME ((REGS32U)0x006000) /* Mailbox enable */
#define CANMD ((REGS32U)0x006002) /* Mailbox direction */
#define CANTRS ((REGS32U)0x006004) /* Transmit request set */
#define CANTRR ((REGS32U)0x006006) /* Transmit request reset */
#define CANTA ((REGS32U)0x006008) /* Transmission acknowledge */
#define CANAA ((REGS32U)0x00600A) /* Abort acknowledge */
#define CANRMP ((REGS32U)0x00600C) /* Receive message pending */
#define CANRML ((REGS32U)0x00600E) /* Receive message lost */
#define CANRFP ((REGS32U)0x006010) /* Remote frame pending */
#define CANGAM ((REGS32U)0x006012) /* Global acceptance mask */
#define CANMC ((REGS32U)0x006014) /* Master control */
#define CANBTC ((REGS32U)0x006016) /* Bit-timing configuration */
#define CANES ((REGS32U)0x006018) /* Error and status */
#define CANTEC ((REGS32U)0x00601A) /* Transmit error counter */
#define CANREC ((REGS32U)0x00601C) /* Receive error counter */
#define CANGIF0 ((REGS32U)0x00601E) /* Global interrupt flag 0 */
#define CANGIM ((REGS32U)0x006020) /* Global interrupt mask */
#define CANGIF1 ((REGS32U)0x006022) /* Global interrupt flag 1 */
#define CANMIM ((REGS32U)0x006024) /* Mailbox interrupt mask */
#define CANMIL ((REGS32U)0x006026) /* Mailbox interrupt level */
#define CANOPC ((REGS32U)0x006028) /* Overwrite protection control */
#define CANTIOC ((REGS32U)0x00602A) /* TX I/O control */
#define CANRIOC ((REGS32U)0x00602C) /* RX I/O control */
#define CANLNT ((REGS32U)0x00602E) /* Local network time (Reserved in SCC mode) */
#define CANTOC ((REGS32U)0x006030) /* Time-out control (Reserved in SCC mode) */
#define CANTOS ((REGS32U)0x006032) /* Time-out status (Reserved in SCC mode) */
#define CANLAM0 ((REGS32U)0x006040) /* 局部屏蔽寄存器CANLAMn , n=0~31 */
#define CANLAM1 ((REGS32U)0x006042)
#define CANLAM2 ((REGS32U)0x006044)
#define CANLAM3 ((REGS32U)0x006046)
#define CANLAM4 ((REGS32U)0x006048)
#define CANLAM5 ((REGS32U)0x00604A)
#define CANLAM6 ((REGS32U)0x00604C)
#define CANLAM7 ((REGS32U)0x00604E)
#define CANLAM8 ((REGS32U)0x006050)
#define CANLAM9 ((REGS32U)0x006052)
#define CANLAM10 ((REGS32U)0x006054)
#define CANLAM11 ((REGS32U)0x006056)
#define CANLAM12 ((REGS32U)0x006058)
#define CANLAM13 ((REGS32U)0x00605A)
#define CANLAM14 ((REGS32U)0x00605C)
#define CANLAM15 ((REGS32U)0x00605E)
#define CANLAM16 ((REGS32U)0x006060)
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